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sharc and the sharc logo are registered trademarks of ana log devices, inc. sharc processor adsp-21477 / adsp-21478 / adsp-21479 rev. c document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without no tice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the proper ty of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106 u.s.a. tel: 781.329.4700 ?2013 analog devices, inc. all rights reserved. technical support www.analog.com summary high performance 32-bit/40-bi t floating-point processor optimized for high performance audio processing single-instruction, multiple-data (simd) computational architecture on-chip memoryup to 5m bits of on-chip ram, 4m bits of on-chip rom up to 300 mhz operating frequency qualified for automotive applications. see automotive prod- ucts on page 75 code compatible with all other members of the sharc family the adsp-2147x processors are available with unique audio-centric peripherals, such as the digital applications interface, serial ports, precision clock generators, s/pdif transceiver, asynchronous samp le rate converters, input data port, and more. factory programmed rom versions containing latest audio decoders from dolby and dts, available to ip licenses for complete ordering information, see ordering guide on page 76 . figure 1. functional block diagram internal memory i/f block 0 ram/rom b0d 64-bit instruction cache 5 stage sequencer pex pey pmd 64-bit iod0 32-bit epd bus 64-bit core bus cross bar s/pdif tx/rx pcg a - d dpi routing/pins spi/b uart block 1 ram/rom block 2 ram block 3 ram ami sdram ctl ep external port pin mux timer 1 - 0 sport 7 - 0 asrc 3 - 0 pwm 3 - 0 dag1/2 core timer pdap/ idp 7 - 0 twi iod0 bus dtcp/ mtm pcg c - d peripheral bus 32-bit core flags/ pwm3 - 1 jtag internal memory dmd 64-bit pmd 64-bit core flags iod1 32-bit peripheral bus b1d 64-bit b2d 64-bit b3d 64-bit dpi peripherals dai peripherals peripherals external port simd core s thermal diode fft fir iir mlb spep bus dmd 64-bit flagx/ irqx / tmrexp wdt rtc shift reg dai routing/pins
rev. c | page 2 of 76 | july 2013 adsp-21477 / adsp-21478 / adsp-21479 table of contents summary ............................................................... 1 general description ................................................. 3 family core architecture ........................................ 4 family peripheral architecture ................................ 8 i/o processor features ......................................... 12 system design .................................................... 13 development tools ............................................. 13 additional information ........................................ 15 related signal chains .......................................... 15 pin function descriptions ....................................... 16 specifications ........................................................ 21 operating conditions .......................................... 21 electrical characteristics ....................................... 22 maximum power dissipation ................................ 24 package information ........................................... 24 esd sensitivity ................................................... 24 absolute maximum ratings ................................... 24 timing specifications ........................................... 25 output drive currents ......................................... 65 test conditions .................................................. 65 capacitive loading .............................................. 65 thermal characteristics ........................................ 66 88-lfcsp_vq lead assignment ................................ 68 100-lqfp_ep lead assignment .. .............................. 70 196-bga ball assignment ........................................ 72 outline dimensions ................................................ 73 surface-mount design .......................................... 75 automotive products ........................................... 75 ordering guide ..................................................... 76 revision history 7/13rev. b to rev. c updated development tools .................................... 13 revised ms 1-0 pin description and v dd_rtc pin description in pin function descriptions ....................................... 16 corrected parameter from i dd-intyp to i dd_int in electrical characteristics .......................................... 22 modified total power dissipation .............................. 23 added footnote 3 to table 32 in ami read .................. 37 changed max values in table 43 in pulse-width modulation generators (pwm) ................................................ 51 corrected the following lead names in table 61 in 88-lfcsp_vq lead assignment ............................... 68 ? clk_cfg_1 to clk_cfg1 ? bootcfg_0 to boot_cfg0 ? bootcfg_1 to boot_cfg1 ? clk_cfg_0 to clk_cfg0 ?xtal2 to xtal updated package outline drawings for 88-lead lfcsp and 100-lead lqfp_ep packages in outline dimensions ..... 73 added automotive model and corrected models in table 64 (automotive product models) in automotive products ... 75 to view product/process change notifications (pcns) related to this data sheet revision, please visit the processors product page on the www.analog.com website and use the view pcn link. product application restriction not for use in in-vivo applications for body fluid constituent monitoring, including monitoring one or more of the compo- nents that form, or may be a part of, or contaminate human blood or other body fluids, such as, but not limited to, car- boxyhemoglobin, methemoglobin total hemoglobin, oxygen saturation, oxygen content, fractional arterial oxygen satura- tion, bilirubin, glucose, drugs, lipids, water, protein, and ph.
adsp-21477 / adsp-21478 / adsp-21479 rev. c | page 3 of 76 | july 2013 general description the adsp-2147x sharc ? processors are members of the simd sharc family of dsps th at feature analog devices super harvard architecture. the processors are source code compatible with the adsp-2 126x, adsp-2136x, adsp-2137x, adsp-2146x, and adsp-2116x dsps as well as with first generation adsp-2106x sharc processors in sisd (single- instruction, single-data) mode . these processors are 32-bit/ 40-bit floating-point processors optimized for high perfor- mance audio applications with a large on-chip sram, multiple internal buses to eliminate i/o bottlenecks, and an innovative digital applications interface (dai). table 1 shows performance benchmarks for the adsp-2147x processors. table 2 shows the features of the individual product offerings. the diagram on page 1 shows the two clock domains (core and i/o processor) that make up the adsp-2147x processors. the core clock domain contains the following features. ? two processing elements (p ex, pey), each of which com- prises an alu, multiplier, shifter, and data register file ? two data address generators (dag1, dag2) ? a program sequencer wi th instruction cache ? pm and dm buses capable of supporting 2 64-bit data transfers between me mory and the core at every core pro- cessor cycle ? one periodic interval timer with pinout ? on-chip sram (up to 5m bit) ? a jtag test access port for emulation and boundary scan. the jtag provides software debug through user break- points, which allows flexible exception handling. table 1. processor benchmarks benchmark algorithm speed (at 300 mhz) speed (at 200 mhz) 1024 point complex fft (radix 4, with reversal) 30.59 s 45.885 s fir filter (per tap) 1 1 assumes two files in multichannel simd mode. 1.66 ns 2.49 ns iir filter (per biquad) 1 6.65 ns 9.975 ns matrix multiply (pipelined) [3 3] [3 1] [4 4] [4 1] 14.99 ns 26.66 ns 22.485 ns 39.99 ns divide (y/) 11.61 ns 17.41 ns inverse square root 18.08 ns 27.12 ns table 2. adsp-2147x family features feature adsp-21477 adsp-21478 adsp-21479 frequency 200 mhz up to 300 mhz ram 2m bits 3m bits 5m bits rom n/a 4m bits pulse-width modulation 3 4 units (3 in 100-lead package) external port interface (sdram, ami) 1 no yes, 16-bit serial ports 8 direct dma from sports to external memory no yes fir, iir, fft accelerator yes medialb interface no automotive models only watch dog timer 2 no yes real-time clock 2, 3 no yes shift register 2 no yes idp/pdap yes uart 1 dai (sru)/dpi (sru2) 20/14 pins s/pdif transceiver 1 spi 2 twi 1 src snr performance C128 db thermal diode 4 yes visa support yes package 1 100-lead lqfp 88-lead lfcsp_vq 196-ball csp_bga 100-lead lqfp 88-lead lfcsp_vq 1 the 100-lead and 88-lead packages of the processors do not contain an external port. the sdram controller pins must be disabled when using this package. for more information, see pin function descriptions on page 17 . 2 available on the 196-ball csp_bga package only. 3 real time clock (rtc) is supported only for products with a temperature range of 0c to +70c and not supported for all other temperature grades. 4 available on the 88-lead and 100-lead packages only. table 2. adsp-2147x family features (continued) feature adsp-21477 adsp-21478 adsp-21479
rev. c | page 4 of 76 | july 2013 adsp-21477 / adsp-21478 / adsp-21479 the block diagram of the adsp-2147x on page 1 also shows the peripheral clock domain (also known as the i/o processor), which contains the following features: ?iod0 (peripheral dma) and iod1 (external port dma) buses for 32-bit data transfers ? peripheral and external port buses for core connection ? external port with an asynchronous memory interface (ami) and sdram controller ?4 units for pulse width modulation (pwm) control ? 1 memory-to-memory (mtm) unit for internal-to-internal memory transfers ? digital applications interface that includes four precision clock generators (pcg), an input data port (idp/pdap) for serial and parallel interconnect, an s/pdif receiver/transmitter, four as ynchronous sample rate con- verters, eight serial ports, a shift register, and a flexible signal routing unit (dai sru). ? digital peripheral interface that includes two timers, a 2- wire interface, one uart, two serial peripheral interfaces (spi), two precision clock generators (pcg), three pulse width modulation (pwm) units, and a flexible signal rout- ing unit (dpi sru). as shown in the sharc core block diagram on page 5 , the pro- cessors use two computational un its to deliver a significant performance increase over the pr evious sharc processors on a range of dsp algorithms. with its simd computational hard- ware, the processors can perform 1.8 gflops running at 300 mhz. family core architecture the processors are code compatib le at the assembly level with the adsp-2146x, adsp-2137x, adsp-2136x, adsp-2126x, adsp-21160, and adsp-21161, an d with the first generation adsp-2106x sharc processors. the adsp-2147x share archi- tectural features with the adsp-2126x, adsp-2136x, adsp- 2137x, adsp-2146x, and adsp- 2116x simd sharc proces- sors, as shown in figure 2 and detailed in the following sections. simd computational engine the processors contain two comp utational processing elements that operate as a single-instruction, multiple-data (simd) engine. the processing elements are referred to as pex and pey and each contains an alu, multiplier, shifter, and register file. pex is always active, and pey may be enabled by setting the peyen mode bit in the mode1 register. simd mode allows the processor to execute the same instruction in both processing elements, but each processing element operates on different data. this architecture is effici ent at executing math intensive dsp algorithms. simd mode also affects the way data is transferred between memory and the processing elem ents because twice the data bandwidth is required to sustai n computational operation in the processing elements. therefore, entering simd mode also dou- bles the bandwidth between memory and the processing elements. when using the dags to transfer data in simd mode, two data values are transf erred with each memory or reg- ister file access. simd mode is supported from external sdram but is not sup- ported in the ami. independent, parallel computation units within each processing element is a set of computational units. the computational units consist of an arithmetic/logic unit (alu), multiplier, and shifter. these units perform all opera- tions in a single cycl e. the three units within each processing element are arranged in paralle l, maximizing computational throughput. single multifunctio n instructions execute parallel alu and multiplier operations . in simd mode, the parallel alu and multiplier operations occur in both processing ele- ments. these computation unit s support ieee 32-bit single- precision floating-point, 40-bit extended precision floating- point, and 32-bit fixed-point data formats. timer the processor contains a core ti mer that can generate periodic software interrupts. the core timer can be configured to use flag3 as a timer expired signal. data register file each processing element contains a general-purpose data regis- ter file. the register files transf er data between the computation units and the data buses, and st ore intermediate results. these 10-port, 32-register (16 primary, 16 secondary) register files, combined with the processors enhanced harvard architecture, allow unconstrained data flow between computation units and internal memory. the registers in pex are referred to as r0Cr15 and in pey as s0Cs15. context switch many of the processors register s have secondary registers that can be activated during interrupt servicing for a fast context switch. the data registers in the register file, the dag registers, and the multiplier result register s all have secondary registers. the primary registers are active at reset, while the secondary registers are activated by control bits in a mode control register. universal registers universal registers can be used for general-purpose tasks. the ustat (4) registers allow easy bit manipulations (set, clear, toggle, test, xor) for all pe ripheral control and status registers. the data bus exchange register (px) permits data to be passed between the 64-bit pm data bus and the 64-bit dm data bus, or between the 40-bit register file and the pm/dm data bus. these registers contain hardware to ha ndle the data width difference. single-cycle fetch of instruction and four operands the processors feature an enhanced harvard architecture in which the data memory (dm) bu s transfers data and the pro- gram memory (pm) bus transfer s both instructions and data (see figure 2 ). with its separate program and data memory
adsp-21477 / adsp-21478 / adsp-21479 rev. c | page 5 of 76 | july 2013 buses and on-chip instruction ca che, the processor can simulta- neously fetch four operands (two over each data bus) and one instruction (from the cache), all in a single cycle. instruction cache the processor includes an on -chip instruction cache that enables three-bus operat ion for fetching an instruction and four data values. the cache is select iveonly the instructions whose fetches conflict with pm bus data accesses are cached. this cache allows full speed execution of core looped operations such as digital filter multiply-a ccumulates, and fft butterfly processing. data address generators wi th zero-overhead hardware circular buffer support the processors two data addre ss generators (dags) are used for indirect addressing and implementing circular data buffers in hardware. circular buffers allow efficient programming of delay lines and other data structures required in digital signal processing, and are commonly used in digital filters and fourier transforms. the two dags of th e processors contain sufficient registers to allow the creation of up to 32 circular buffers (16 primary register sets, 16 second ary). the dags automatically handle address pointer wraparound, reduce overhead, increase performance, and simplify implem entation. circular buffers can start and end at any memory location. flexible instruction set the 48-bit instruction word acco mmodates a variety of parallel operations, for concise prog ramming. for example, the processors can conditionally execute a multiply, an add, and a subtract in both processing elements while branching and fetch- ing up to four 32-bit values from memoryall in a single instruction. variable instruction set architecture (visa) in addition to supporting the st andard 48-bit instructions from previous sharc processors, the processors support new instructions of 16 and 32 bits. this feature, called variable instruction set architecture (visa), drops redundant/unused figure 2. sharc co re block diagram s simd core cache interrupt 5 stage program sequencer pm address 32 dm address 32 dm data 64 pm data 64 dag1 1632 mrf 80-bit alu multiplier shifter rf rx/fx pex 1640-bit jtag dmd/pmd 64 astatx stykx astaty styky timer rf sx/sfx pey 1640-bit mrb 80-bit msb 80-bit msf 80-bit flag system i/f ustat 432-bit px 64-bit dag2 1632 alu multiplier shifter data swap pm address 24 pm data 48
rev. c | page 6 of 76 | july 2013 adsp-21477 / adsp-21478 / adsp-21479 bits within the 48-bit instruction to create more efficient and compact code. the program sequ encer supports fetching these 16-bit and 32-bit instructions from both internal and external sdram memory. this support is not extended to the asynchro- nous memory interface (ami). source modules need to be built using the visa option, in order to allow code generation tools to create these more efficient opcodes. on-chip memory the processors contain varying amounts of internal ram and internal rom which is shown in table 3 through table 5 . each block can be configured for diffe rent combinations of code and data storage. each memory bl ock supports single-cycle, inde- pendent accesses by the core processor and i/o processor. the processors sram can be configured as a maximum of 160k words of 32-bit data, 320k words of 16-bit data, 106.7k words of 48-bit instructions (or 40 -bit data), or combinations of different word sizes up to 5m bits. all of the memory can be accessed as 16-bit, 32-bit, 48-bi t, or 64-bit words. a 16-bit floating-point storage format is supported that effectively dou- bles the amount of data that may be stored on-chip. conversion between the 32-bit floating-point and 16-bit floating-point formats is performed in a single instruction. while each mem- ory block can store combinations of code and data, accesses are most efficient when one block st ores data using the dm bus for transfers, and the other block stor es instructions and data using the pm bus for transfers. using the dm bus and pm buses, with one bus dedicated to a memory block, assures single-c ycle execution with two data transfers. in this ca se, the instruction must be available in the cache. the memory maps in table 3 through table 5 display the inter- nal memory address space of th e processors. the 48-bit space section describes what this ad dress range looks like to an instruction that retrieves 48- bit memory. the 32-bit section describes what this address rang e looks like to an instruction that retrieves 32-bit memory. table 3. adsp-21477 internal memory space (2m bits) iop registers 0x0000 0000C0x0003 ffff long word (64 bits) extended precision normal or instruction word (48 bits) normal word (32 bits) short word (16 bits) block 0 rom (reserved) 0x0004 0000C0x0004 7fff block 0 rom (reserved) 0x0008 0000C0x0008 aaa9 block 0 rom (reserved) 0x0008 0000C0x0008 ffff block 0 rom (reserved) 0x0010 0000C0x0011 ffff reserved 0x0004 8000C0x0004 8fff reserved 0x0008 aaaaC0x0008 bfff reserved 0x0009 0000C0x0009 1fff reserved 0x0012 0000C0x0012 ffff block 0 sram 0x0004 9000C0x0004 bfff block 0 sram 0x0008 c000C0x0008 ffff block 0 sram 0x0009 2000C0x0009 7fff block 0 sram 0x0012 4000C0x0012 ffff reserved 0x0004 c000C0x0004 ffff reserved 0x0009 000C0x0009 5554 reserved 0x0009 8000C0x0009 ffff reserved 0x0013 0000C0x0013 ffff block 1 rom (reserved) 0x0005 0000C0x0005 7fff block 1 rom (reserved) 0x000a 0000C0x000a aaa9 block 1 rom (reserved) 0x000a 0000C0x000affff block 1 rom (reserved) 0x0014 0000C0x0015 ffff reserved 0x0005 8000C0x0005 8fff reserved 0x000a aaaaC0x000a bfff reserved 0x000b 0000C0x000b 1fff reserved 0x0016 0000C0x0016 3fff block 1 sram 0x0005 9000C0x0005 bfff block 1 sram 0x000a c000C0x000a ffff block 1 sram 0x000b 2000C0x000b 7fff block 1 sram 0x0016 4000C0x0016 ffff reserved 0x0005 c000C0x0005 ffff reserved 0x000b 0000C0x000b 5554 reserved 0x000b 8000C0x000b ffff reserved 0x0017 0000C0x0017 ffff block 2 sram 0x0006 0000C0x0006 0fff block 2 sram 0x000c 0000C0x000c 1554 block 2 sram 0x000c 0000C0x000c 1fff block 2 sram 0x0018 0000C0x0018 3fff reserved 0x0006 1000C 0x0006 ffff reserved 0x000c 1555C0x000d 5554 reserved 0x000c 2000C0x000d ffff reserved 0x0018 4000C0x001b ffff block 3 sram 0x0007 0000C0x0007 0fff block 3 sram 0x000e 0000C0x000e 1554 block 3 sram 0x000e 0000C0x000e 1fff block 3 sram 0x001c 0000C0x001c 3fff reserved 0x0007 1000C0x0007 ffff reserved 0x000e 1555C0x000f 5554 reserved 0x000e 2000C0x000f ffff reserved 0x001c 4000C0x001f ffff
adsp-21477 / adsp-21478 / adsp-21479 rev. c | page 7 of 76 | july 2013 table 4. adsp-21478 internal memory space (3m bits) 1 iop registers 0x0000 0000C0x0003 ffff long word (64 bits) extended precision normal or instruction word (48 bits) normal word (32 bits) short word (16 bits) block 0 rom (reserved) 0x0004 0000C0x0004 7fff block 0 rom (reserved) 0x0008 0000C0x0008 aaa9 block 0 rom (reserved) 0x0008 0000C0x0008 ffff block 0 rom (reserved) 0x0010 0000C0x0011 ffff reserved 0x0004 8000C0x0004 8fff reserved 0x0008 aaaaC0x0008 bfff reserved 0x0009 0000C0x0009 1fff reserved 0x0012 0000C0x0012 3fff block 0 sram 0x0004 9000C0x0004 cfff block 0 sram 0x0008 c000C0x0009 1554 block 0 sram 0x0009 2000C0x0009 9fff block 0 sram 0x0012 4000C0x0013 3fff reserved 0x0004 d000C0x0004 ffff reserved 0x0009 1555C0x0009 ffff reserved 0x0009 a000C0x0009 ffff reserved 0x0013 4000C0x0013 ffff block 1 rom (reserved) 0x0005 0000C0x0005 7fff block 1 rom (reserved) 0x000a 0000C0x000a aaa9 block 1 rom (reserved) 0x000a 0000C0x000a ffff block 1 rom (reserved) 0x0014 0000C0x0015 ffff reserved 0x0005 8000C0x0005 8fff reserved 0x000a aaaaC0x000a bfff reserved 0x000b 0000C0x000b 1fff reserved 0x0016 0000C0x0016 3fff block 1 sram 0x0005 9000C0x0005 cfff block 1 sram 0x000a c000C0x000b 1554 block 1 sram 0x000b 2000C0x000b 9fff block 1 sram 0x0016 4000C0x0017 3fff reserved 0x0005 d000C0x0005 ffff reserved 0x000b 1555C0x000b ffff reserved 0x000b a000C0x000b ffff reserved 0x0017 4000C0x0017 ffff block 2 sram 0x0006 0000C0x0006 1fff block 2 sram 0x000c 0000C0x000c 2aa9 block 2 sram 0x000c 0000C0x000c 3fff block 2 sram 0x0018 0000C0x0018 7fff reserved 0x0006 2000C 0x0006 ffff reserved 0x000c 2aaaC0x000d ffff reserved 0x000c 4000C0x000d ffff reserved 0x0018 8000C0x001b ffff block 3 sram 0x0007 0000C0x0007 1fff block 3 sram 0x000e 0000C0x000e 2aa9 block 3 sram 0x000e 0000C0x000e 3fff block 3 sram 0x001c 0000C0x001c 7fff reserved 0x0007 2000C0x0007 ffff reserved 0x000e 2aaaC0x000f ffff reserved 0x000e 4000C0x000f ffff reserved 0x001c 8000C0x001f ffff 1 some processors include a customer-definable rom block. rom addresses on these models are not reserved as shown in this table. please contact your analog devices sales representative for additional details.
rev. c | page 8 of 76 | july 2013 adsp-21477 / adsp-21478 / adsp-21479 on-chip memory bandwidth the internal memory architecture allows programs to have four accesses at the same time to an y of the four blocks (assuming there are no block conflicts). th e total bandwidth is realized using the dmd and pmd buses (2 64-bit at cclk speed) and the iod0/1 buses (2 32-bit at pclk speed). rom based security the processors have a rom security feature that provides hard- ware support for securing user software code by preventing unauthorized reading from the in ternal code. when using this feature, the processors do not boot-load any external code, exe- cuting exclusively from inte rnal rom. additionally, the processor is not freely accessibl e via the jtag port. instead, a unique 64-bit key, which must be scanned in through the jtag or test access port, is assigned to each custom er. the device ignores an incorrect key. emulation features are available after the correct key is scanned. digital transmission content protection the dtcp specification defines a cryptographic protocol for protecting audio entertainment content from illegal copying, intercepting, and tampering as it traverses high performance digital buses, such as the ieee 1394 standard. only legitimate entertainment content delivered to a source device via another approved copy protection syst em (such as the dvd content scrambling system) is protected by this copy prot ection system. for more information on this feature, contact your local adi sales office. family peripheral architecture the adsp-2147x family contains a rich set of peripherals that support a wide variety of applications including high quality audio, medical imaging, communications, military, test equip- ment, 3d graphics, speech recognit ion, motor control, imaging, and other applications. table 5. adsp-21479 internal memory space (5m bits) 1 iop registers 0x0000 0000C0x0003 ffff long word (64 bits) extended precision normal or instruction word (48 bits) normal word (32 bits) short word (16 bits) block 0 rom (reserved) 0x0004 0000C0x0004 7fff block 0 rom (reserved) 0x0008 0000C0x0008 aaa9 block 0 rom (reserved) 0x0008 0000C0x0008 ffff block 0 rom (reserved) 0x0010 0000C0x0011 ffff reserved 0x0004 8000C0x0004 8fff reserved 0x0008 aaaaC0x0008 bfff reserved 0x0009 0000C0x0009 1fff reserved 0x0012 0000C0x0012 3fff block 0 sram 0x0004 9000C0x0004 efff block 0 sram 0x0008 c000C0x0009 3fff block 0 sram 0x0009 2000C0x0009 dfff block 0 sram 0x0012 4000C0x0013 bfff reserved 0x0004 f000C0x0004 ffff reserved 0x0009 4000C0x0009 ffff reserved 0x0009 e000C0x0009 ffff reserved 0x0013 c000C0x0013 ffff block 1 rom (reserved) 0x0005 0000C0x0005 7fff block 1 rom (reserved) 0x000a 0000C0x000a aaa9 block 1 rom (reserved) 0x000a 0000C0x000affff block 1 rom (reserved) 0x0014 0000C0x0015 ffff reserved 0x0005 8000C0x0005 8fff reserved 0x000a aaaaC0x000a bfff reserved 0x000b 0000C0x000b 1fff reserved 0x0016 0000C0x0016 3fff block 1 sram 0x0005 9000C0x0005 efff block 1 sram 0x000a c000C0x000b 3fff block 1 sram 0x000b 2000C0x000b dfff block 1 sram 0x0016 4000C0x0017 bfff reserved 0x0005 f000C0x0005 ffff reserved 0x000b 4000C0x000b ffff reserved 0x000b e000C0x000b ffff reserved 0x0017 c000C0x0017 ffff block 2 sram 0x0006 0000C0x0006 3fff block 2 sram 0x000c 0000C0x000c 5554 block 2 sram 0x000c 0000C0x000c 7fff block 2 sram 0x0018 0000C0x0018 ffff reserved 0x0006 4000C 0x0006 ffff reserved 0x000c 5555C0x0000d ffff reserved 0x000c 8000C0x000d ffff reserved 0x0019 0000C0x001b ffff block 3 sram 0x0007 0000C0x0007 3fff block 3 sram 0x000e 0000C0x000e 5554 block 3 sram 0x000e 0000C0x000e 7fff block 3 sram 0x001c 0000C0x001c ffff reserved 0x0007 4000C0x0007 ffff reserved 0x000e 5555C0x0000f ffff reserved 0x000e 8000C0x000f ffff reserved 0x001d 0000C0x001f ffff 1 some processors include a customer-definable rom block. rom addres ses on these models are not reserved as shown in this table. please contact your analog devices sales representative for additional details.
adsp-21477 / adsp-21478 / adsp-21479 rev. c | page 9 of 76 | july 2013 external memory the external memory interface su pports access to the external memory through core and dma accesses. the external memory address space is divided into four banks. any bank can be pro- grammed as either asynchronous or synchronous memory. the external ports are comprise d of the following modules. ? an ami which communicates with sram, flash, and other devices that meet the standard asynchronous sram access protocol. the ami supports 6m words of external memory in bank 0 and 8m words of external memory in bank 1, bank 2, and bank 3. ? an sdram controller that supports a glueless interface with any of the standard sdrams. the sdc supports 62m words of external memory in bank 0, and 64m words of external memory in bank 1, bank 2, and bank 3. ? arbitration logic to coordinate core and dma transfers between internal and external memory over the external port. external port the external port provides a hi gh performance, glueless inter- face to a wide variety of industry-standard memory devices. the external port, available on th e 196-ball csp_bga, may be used to interface to synchronous and/or asynchronous memory devices through the use of its se parate internal memory control- lers. the first is an sdram controller for connection of industry-standard sy nchronous dram devices while the sec- ond is an asynchronous memory controller intended to interface to a variety of memory devices. four memory select pins enable up to four separate devices to coexist, supporting any desired combination of synchronous and asynchronous device types. non-sdram extern al memory address space is shown in table 6 . simd access to external memory the sdram controller supports simd access on the 64-bit external port data bus (epd) wh ich allows access to the comple- mentary registers on the pey un it in the normal word space (nw). this improves performanc e since there is no need to explicitly load the complementar y registers (as in sisd mode). visa and isa access to external memory the sdram controller supports visa code operation which reduces the memory load since the visa instructions are com- pressed. moreover, bus fetching is reduced because, in the best case, one 48-bit fetch contains three valid instructions. code execution from the traditional is a operation is also supported. note that code execution is only supported from bank 0 regard- less of visa/isa. table 7 shows the address ranges for instruction fetch in each mode. sdram controller the sdram controller, availabl e on the adsp-2147x in the 196-ball csp_bga package, provides an interface of up to four separate banks of industry -standard sdram devices or dimms, at speeds up to f sdclk . fully compliant with the sdram standard, each bank has its own memory select line (ms0 Cms3 ), and can be configured to contain between 4 mbytes and 256 mbytes of memory. sdram external mem- ory address space is shown in table 8 . a set of programmable timing parameters is available to config- ure the sdram banks to support slower memory devices. the sdram and the ami interface do not support 32-bit wide devices. the sdram controller address, data, clock, and control pins can drive loads up to distributed 30 pf. for larger memory sys- tems, the sdram controller external buffer timing should be selected and external buffering sh ould be provided so that the load on the sdram controller pins does not exceed 30 pf. note that the external memory bank addresse s shown are for normal-word (32-bit) accesses. if 48-bit instructions as well as 32-bit data are both placed in the same external memory bank, care must be taken while mapping them to avoid overlap. asynchronous memory controller the asynchronous memory controller, available on the adsp-2147x in the 196-ball csp_bga package, provides a con- figurable interface for up to four separate banks of memory or i/o devices. each bank can be independently programmed with different timing parameters, enabli ng connection to a wide vari- ety of memory devices including sram, flash, and eprom, as well as i/o devices that interface with standard memory control lines. bank 0 occupies a 6m word window and banks 1, 2, and 3 table 6. external memory for non-sdram addresses bank size in words address range bank 0 6m 0x0020 0000C0x007f ffff bank 1 8m 0x0400 0000C0x047f ffff bank 2 8m 0x0800 0000C0x087f ffff bank 3 8m 0x0c00 0000C0x0c7f ffff table 7. external bank 0 instruction fetch access type size in words address range isa (nw) 4m 0x0020 0000C0x005f ffff visa (sw) 10m 0x0060 0000C0x00ff ffff table 8. external memory for sdram addresses bank size in words address range bank 0 62m 0x0020 0000C0x03ff ffff bank 1 64m 0x0400 0000C0x07ff ffff bank 2 64m 0x0800 0000C0x0bff ffff bank 3 64m 0x0c00 0000C0x0fff ffff
rev. c | page 10 of 76 | july 2013 adsp-21477 / adsp-21478 / adsp-21479 occupy a 8m word window in th e processors address space but, if not fully populated, these windows are not made contiguous by the memory controller logic. external port throughput the throughput for the external port, based on 133 mhz clock and 16-bit data bus, is 88 mbytes/sec for the ami and 266 mbytes/sec for sdram. medialb the automotive models of the processors have an mlb interface which allows the processor to function as a media local bus device. it includes support for both 3-pin and 5-pin mlb proto- cols. it supports speeds up to 1024 fs (49.25m bits/sec, fs = 48.1 khz) and up to 31 logical channels, with up to 124 bytes of data per me dia local bus frame. for a list of auto- motive products, see automotive products on page 75 . digital applications interface (dai) the digital applications interface (dai) provides the ability to connect various peripherals to any of the dai pins (dai_p20C1). programs make these connections using the signal routing unit (sru), shown in figure 1 . the sru is a matrix routing unit (or group of multiplexers) that enables the peripherals provided by the dai to be intercon- nected under software control. th is allows easy use of the dai associated peripherals for a much wider variety of applications by using a larger set of algorithms than is possible with non con- figurable signal paths. the associated peripherals include eight serial ports, four preci- sion clock generators (pcg), a s/pdif transceiver, four asrcs, and an input data port (idp). the idp provides an additional input path to the sharc core, configurable as either eight channels of serial data, or a si ngle 20-bit wide synchronous par- allel data acquisition port. each data channel has its own dma channel that is independent from the processors serial ports. serial ports (sports) the processors feature eight sync hronous serial ports that pro- vide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices such as analog devices ad183x family of audio codecs , adcs, and dacs. the serial ports are made up of two data lines, a clock, and frame sync. the data lines can be programmed to either transmit or receive and each data line has a dedicated dma channel. serial ports can support up to 16 transmit or 16 receive dma channels of audio data when a ll eight sports are enabled, or four full duplex tdm stream s of 128 channels per frame. serial port data can be automa tically transferred to and from on-chip memory/external memory via dedicated dma chan- nels. each of the serial ports can work in conjunction with another serial port to prov ide tdm support. one sport pro- vides two transmit signals whil e the other sport provides the two receive signals. the frame sync and clock are shared. serial ports operate in five modes: ? standard serial mode ?multichannel (tdm) mode ?i 2 s mode ?packed i 2 s mode ? left-justified mode s/pdif-compatible digital audio receiver/transmitter the s/pdif receiver/transmitter has no separate dma chan- nels. it receives audio data in serial format and converts it into a bi phase encoded signal. the serial data input to the receiver/transmitter ca n be formatted as left justified, i 2 s or right-justified with word widths of 16, 18, 20, or 24 bits. the serial data, clock, and fram e sync inputs to the s/pdif receiver/transmitter are routed th rough the signal routing unit (sru). they can come from a va riety of sources, such as the sports, external pins, the precision clock generators (pcgs), and are controlled by the sru control registers. asynchronous sample rate converter (src) the sample rate converter contains four blocks and is the same core as that used in the ad 1896 192 khz stereo asynchronous sample rate converter. the sr c block provides up to 128 db snr and is used to perform synchronous or asynchronous sam- ple rate conversion across indepe ndent stereo channels, without using internal processor resour ces. the four src blocks can also be configured to operate to gether to convert multichannel audio data without phase mismatches. finally, the src can be used to clean up audio data from jittery clock sources such as the s/pdif receiver. input data port the idp provides up to eight se rial input channelseach with its own clock, frame sync, and data inputs. the eight channels are automatically multiplexed into a single 32-bit by eight-deep fifo. data is always formatted as a 64-bit frame and divided into two 32-bit words. the serial protocol is designed to receive audio channels in i 2 s, left-justified sample pair, or right-justified mode. the idp also provides a parallel data acquisition port (pdap) which can be used for receivin g parallel data. the pdap port has a clock input and a hold input. the data for the pdap can be received from dai pins or fr om the external port pins. the pdap supports a maximum of 20-bit data and four different packing modes to receiv e the incoming data. precision clock generators the precision clock generators (pcg) consist of four units, each of which generates a pair of signals (clock and frame sync) derived from a clock input signal. the units, a b, c, and d are identical in functionality and operate independently of each other. the two signals generated by each unit are normally used as a serial bit clock/frame sync pair. the outputs of pcg a and b ca n be routed through the dai pins and the outputs of pcg c and d can be driven on to the dai as well as the dpi pins.
adsp-21477 / adsp-21478 / adsp-21479 rev. c | page 11 of 76 | july 2013 digital peripheral interface (dpi) the digital peripheral interfac e provides connections to two serial peripheral interface port s (spi), one universal asynchro- nous receiver-transmitter (uart) , 12 flags, a 2-wire interface (twi), three pwm modules (pwm3C1), and two general- purpose timers. serial peripheral (compatible) interface (spi) the spi is an industry-stand ard synchronous serial link, enabling the spi-compatible po rt to communicate with other spi compatible devices. the spi consists of two data pins, one device select pin, and one clock pin. it is a full-duplex synchro- nous serial interface, supportin g both master and slave modes. the spi port can operate in a multi-master environment by interfacing with up to four othe r spi-compatible devices, either acting as a master or slave device. the spi-compatible periph- eral implementation also features programmable baud rate and clock phase and polarities. the spi-compatible port uses open drain drivers to support a mult i-master configuration and to avoid data contention. uart port the processors provide a full-duplex universal asynchronous receiver/transmitter (uart) port , which is fully compatible with pc-standard uarts. the uart port provides a simpli- fied uart interface to other pe ripherals or hosts, supporting full-duplex, dma-supported, asynch ronous transfers of serial data. the uart also has mult iprocessor communication capa- bility using 9-bit address detection. this allows it to be used in multidrop networks through the rs-485 data interface standard. the uart port also in cludes support for 5 to 8 data bits, 1 or 2 stop bits, and none, even, or odd parity. the uart port supports two modes of operation: ? pio (programmed i/o) C the processor sends or receives data by writing or reading i/o-mapped uart registers. the data is double-buffered on both transmit and receive. ? dma (direct memory access) C the dma controller trans- fers both transmit and receive data. this reduces the number and frequency of interr upts required to transfer data to and from memory. the uart has two dedicated dma channels, one for transmit and one for receive. these dma channels have lower default priority than most dma channels because of their re latively low service rates. the uart port's baud rate, seri al data format, error code gen- eration and status, and interrupts are programmable: ? support for bit rates ranging from (f pclk /1,048,576) to (f pclk /16) bits per second. ? support for data formats fr om 7 to 12 bits per frame. ? both transmit and receive oper ations can be configured to generate maskable interrupts to the processor. in conjunction with the general-purpose timer functions, auto- baud detection is supported. pulse-width modulation the pwm module is a flexible , programmable, pwm waveform generator that can be programm ed to generate the required switching patterns for various appl ications related to motor and engine control or audio power control. the pwm generator can generate either center-aligned or edge-aligned pwm wave- forms. in addition, it can gene rate complementary signals on two outputs in paired mode or independent signals in non- paired mode (applic able to a single group of four pwm waveforms). the entire pwm module has four groups of four pwm outputs generating 16 pwm outputs in total. each pwm group pro- duces two pairs of pwm signal s on the four pwm outputs. the pwm generator is capable of operating in two distinct modes while generating center-aligned pwm waveforms: single update mode or double update mode. in single update mode the duty cycle values are programmab le only once per pwm period. this results in pwm patterns that are symmetrical about the midpoint of the pwm period. in double update mode, a second updating of the pwm registers is implemented at the midpoint of the pwm period. in this mo de, it is possible to produce asymmetrical pwm patterns that produce lower harmonic dis- tortion in three-ph ase pwm inverters. pwm signals can be mapped to th e external port address lines or to the dpi pins. timers the processors have a total of th ree timers: a core timer that can generate periodic software interrupts and two general-purpose timers that can generate peri odic interrupts and be inde- pendently set to operate in one of three modes: ?pulse waveform generation mode ?pulse width co unt/capture mode ? external event watch dog mode the core timer can be configured to use flag3 as a timer expired signal, and the general-pu rpose timers have one bidirec- tional pin and four registers that implement its mode of operation: a 6-bit configuration register, a 32-bit count register, a 32-bit period regist er, and a 32-bit pulse width register. a sin- gle control and status register enables or disables the general- purpose timer. 2-wire interface port (twi) the twi is a bidirectional 2-wire serial bus used to move 8-bit data while maintaining compliance with the i 2 c bus protocol. the twi master incorporates the following features: ? 7-bit addressing ? simultaneous master and slave operation on multiple device systems with suppor t for multi-master data arbitration ? digital filtering and timed event processing ? 100 kbps and 400 kbps data rates ? low interrupt rate
rev. c | page 12 of 76 | july 2013 adsp-21477 / adsp-21478 / adsp-21479 shift register the shift register can be used as a serial to parallel data con- verter. the shift register module consists of an 18-stage serial shift register, 18-bit latch, and three-state output buffers. the shift register and latch have separate clocks. data is shifted into the serial shift register on the positive-going transitions of the shift register serial clock (sr_ sclk) input. the data in each flip-flop is transferred to the respective latch on a positive-going transition of the shift register latch clock (sr_lat) input. the shift registers signals ca n be configured as follows. ? the sr_sclk can come from any of the sport0C7 sclk outputs, pcga/b clock, any of the dai pins (1C8), and one dedicated pin (sr_sclk). ? the sr_lat can come from any of sport0C7 frame sync outputs, pcga/b frame sync, any of the dai pins (1C8), and one dedicated pin (sr_lat). ? the sr_sdi input can from any of sport0C7 serial data outputs, any of the dai pins (1C8), and one dedicated pin (sr_sdi). note that the sr_sclk, sr_lat, and sr_sdi inputs must come from same source except in the case of where sr_sclk comes from pcga/b or sr_sclk and sr_lat come from pcga/b. if sr_sclk comes from pcga/b , then sport0C7 generates the sr_lat and sr_sdi signals. if sr_sclk and sr_lat come from pcga/b, then sport0C7 generates the sr_sdi signal. i/o processor features the i/o processor provides up to 65 channels of dma as well as an extensive set of peripherals. dma controller the dma controller operates in dependently and invisibly to the processor core, allowing dma operations to occur while the core is simultaneously executin g its program instructions. dma transfers can occur between the processors internal memory and its serial ports, the spi-comp atible (serial peripheral inter- face) ports, the idp (input da ta port), the parallel data acquisition port (pdap) or the uart. up to 65 channels of dma are available on the processors as shown in table 9 . programs can be downloaded using dma transfers. other dma features include interrupt ge neration upon completion of dma transfers, and dma chaini ng for automatic linked dma transfers. delay line dma the processor provides delay line dma functionality. this allows processor reads and writes to external delay line buffers (and therefore to external memory) with limited core interaction. scatter/gather dma the processor provides scatter/ga ther dma functionality. this allows processor dma reads/wr ites to/from noncontiguous memory blocks. fft accelerator the fft accelerator implements radix-2 complex/real input, complex output ffts with no co re intervention. the fft accel- erator runs at the peripheral clock frequency. fir accelerator the fir (finite impulse response ) accelerator consists of a 1024 word coefficient memo ry, a 1024 word deep delay line for the data, and four mac units. a controller manages the accelerator. the fir accelerator runs at the peripheral clock frequency. iir accelerator the iir (infinite impulse respon se) accelerator consists of a 1440 word coefficient memory fo r storage of biquad coeffi- cients, a data memory for storin g the intermediate data and one mac unit. a controller manages th e accelerator. the iir accel- erator runs at the peripheral clock frequency. watchdog timer (wdt) the processors include a 32-bit wa tchdog timer that can be used to implement a software watchdog function. a software watch- dog can improve system reliability by forcing the processor to a known state through generation of a system reset if the timer expires before being re loaded by software. software initializes the count value of the timer, and then enables the timer. the wdt is used to supervise th e stability of the system soft- ware. when used in this way, software reloads the wdt in a regular manner so that the do wnward counting timer never expires. an expiring timer then indicates that system software might be out of control. the wdt resets both the core and the internal peripherals. software must be able to determine if the watch dog was the source of the hardware reset by interrogating a status bit in the watch dog timer control register. table 9. dma channels peripheral dma channels sports 16 pdap 8 spi 2 uart 2 external port 2 accelerators 2 memory-to-memory 2 medialb 1 31 1 automotive models only. table 9. dma channels (continued) peripheral dma channels
adsp-21477 / adsp-21478 / adsp-21479 rev. c | page 13 of 76 | july 2013 the watch dog timer also has an internal rc oscillator that can be used as the clock source. the internal rc oscillator can be used as an optional alternative to using an external clock applied to the wdt_clin pin. real-time clock the real-time clock (rtc) provides a robust set of digital watch features, including current time, stopwatch, and alarm. the rtc is clocked by a 32.768 khz cr ystal external to the sharc processor. connect rtc pins rt xi and rtxo with external components as shown in figure 3 . the rtc peripheral has dedicated power supply pins so that it can remain powered up and clocked even when the rest of the processor is in a low power stat e. the rtc provides several pro- grammable interrupt options, including interrupt per second, minute, hour, or day clock ticks, interrupt on programmable stopwatch countdown, or interrupt at a programmed alarm time. an rtclkout signal that operates at 1 hz is also pro- vided for calibration. the 32.768 khz input clock frequency is divided down to a 1 hz signal by a prescaler. the counter function of the timer consists of four counters: a 60-second co unter, a 60-minute counter, a 24-hour counter, and a 32,768-d ay counter. when the alarm interrupt is enabled, the alarm function generates an interrupt when the output of the timer ma tches the programmed value in the alarm control register. there are two alarms: the first alarm is for a time of day. the second alarm is for a day and time of that day. the stopwatch function counts down from a programmed value, with one-second resolu tion. when the stopwatch inter- rupt is enabled and the counte r underflows, an interrupt is generated. system design the following sections provide an introduction to system design options and power supply issues. program booting the internal memory boots at sy stem power-up from an 8-bit eprom via the external port, an spi master, or an spi slave. booting is determined by the boot configuration (boot_cfg2C0) pins in table 10 . a running reset feature is used to reset the processor core and peripherals without resetting the pll and sdram controller, or performing a boot. the fu nctionality of the resetout /runrstin pin has now been extended to also act as the input for initiating a running reset. for more information, see the adsp-214xx sharc processor hardware reference . power supplies the processors have separate power supply connections for the internal (v dd_int ) and external (v dd_ext ) power supplies. the internal and analog supplies must meet the v dd_int specifica- tions. the external supply must meet the v dd_ext specification. all external supply pins must be connected to the same power supply. to reduce noise coupling, the pc b should use a parallel pair of power and ground planes for v dd_int and gnd. target board jtag emulator connector analog devices dsp tools product line of jtag emulators uses the ieee 1149.1 jtag test access port of the processors to mon- itor and control the target board processor during emulation. analog devices dsp tools product line of jtag emulators pro- vides emulation at full processor speed, allowing inspection and modification of memory, regist ers, and processor stacks. the processor's jtag interface ensu res that the emulator will not affect target system loading or timing. for complete information on analog devices sharc dsp tools product line of jtag emulator operation, see the appro- priate emulator hardware users guide. development tools analog devices supports its proce ssors with a complete line of software and hardware development tools, including integrated development environments (which include crosscore ? embed- ded studio and/or visualdsp++ ? ), evaluation products, emulators, and a wide variety of software add-ins. integrated development environments (ides) for c/c++ software writing and editing, code generation, and debug support, analog devices offers two ides. the newest ide, crosscore embe dded studio, is based on the eclipse tm framework. supporting most analog devices proces- sor families, it is the ide of choice for future processors, including multicore devices. crosscore embedded studio figure 3. external components for rtc rtxo c1 c2 x1 note: c1 and c2 are specific to crystal specified for x1. contact crystal manufacturer for details. c1 and c2 specifications assume board trace capacitance of 3 pf. rtxi r1 table 10. boot mode selection boot_cfg2C0 1 booting mode 000 spi slave boot 001 spi master boot (from flash and other slaves) 010 ami user boot (for 8-bit flash boot) 011 no boot (processor executes from internal rom after reset) 100 reserved 1xx reserved 1 the boot_cfg2 pin is not available on the 100-lead or 88-lead packages.
rev. c | page 14 of 76 | july 2013 adsp-21477 / adsp-21478 / adsp-21479 seamlessly integrates available software add-ins to support real time operating systems, file systems, tcp/ip stacks, usb stacks, algorithmic software modules, and evaluation hardware board support packages. for more information visit www.analog.com/cces . the other analog devices ide, visualdsp++, supports proces- sor families introduced prior to the release of crosscore embedded studio. this ide includes the analog devices vdk real time operating system and an open source tcp/ip stack. for more information visit www.analog.com/visualdsp . note that visualdsp++ will not support future analog devices processors. ez-kit lite evaluation board for processor evaluation, analog devices provides wide range of ez-kit lite ? evaluation boards. incl uding the pr ocessor and key peripherals, the evaluation board also supports on-chip emulation capabilities and other evaluation and development features. also available are various ez-extenders ? , which are daughter cards delivering additional specialized functionality, including audio and video processing. for more information visit www.analog.com and search on ezkit or ezextender. ez-kit lite evaluation kits for a cost-effective way to lear n more about developing with analog devices processors, analog devices offer a range of ez- kit lite evaluation kits. each evaluation kit includes an ez-kit lite evaluation board, directions for downloading an evaluation version of the available ide(s), a usb cable, and a power supply. the usb controller on the ez-kit lite board connects to the usb port of the users pc, enab ling the chosen ide evaluation suite to emulate the on-board processor in-circuit. this permits the customer to download, execut e, and debug programs for the ez-kit lite system. it also su pports in-circuit programming of the on-board flash device to store user-specific boot code, enabling standalone operation. with the full version of cross- core embedded studio or visualdsp++ installed (sold separately), engineers can deve lop software for supported ez- kits or any custom system util izing supported analog devices processors. software add-ins for cr osscore embedded studio analog devices offers software add-ins which seamlessly inte- grate with crosscore embedded stud io to extend its capabilities and reduce development time. add-ins include board support packages for evaluation hardwa re, various middleware pack- ages, and algorithmic modules. documentation, help, configuration dialogs, and coding examples present in these add-ins are viewable through th e crosscore embedded studio ide once the add-in is installed. board support packages for evaluation hardware software support for the ez-kit lite evaluation boards and ez- extender daughter cards is prov ided by software add-ins called board support packages (bsps). the bsps contain the required drivers, pertinent release notes, and select example code for the given evaluation hardware. a downlo ad link for a specific bsp is located on the web page for th e associated ez-kit or ez- extender product. the link is found in the product download area of the product web page. middleware packages analog devices separately offers middleware add-ins such as real time operating systems, file systems, usb stacks, and tcp/ip stacks. for more info rmation see the following web pages: ? www.analog.com/ucos3 ? www.analog.com/ucfs ? www.analog.com/ucusbd ? www.analog.com/lwip algorithmic modules to speed development, analog devices offers add-ins that per- form popular audio and video pr ocessing algorithms. these are available for use with both cr osscore embedded studio and visualdsp++. for more information visit www.analog.com and search on blackfin software modules or sharc software modules. designing an emulator-compatible dsp board (target) for embedded system test and debug, analog devices provides a family of emulators. on each jtag dsp, analog devices sup- plies an ieee 1149.1 jtag test access port (tap). in-circuit emulation is facilitated by use of this jtag interface. the emu- lator accesses the processors internal features via the processors tap, allowing the de veloper to load code, set break- points, and view variables, memory, and registers. the processor must be halted to se nd data and commands, but once an operation is completed by the emulator, the dsp system is set to run at full speed with no im pact on system timing. the emu- lators require the target board to include a header that supports connection of the dsps jt ag port to the emulator. for details on target board desi gn issues including mechanical layout, single processor connection s, signal buffering, signal ter- mination, and emulator pod logic, see the ee-68: analog devices jtag emulation technical reference on the analog devices website ( www.analog.com )use site search on ee-68. this document is updated regularly to keep pace with improvements to emulator support.
adsp-21477 / adsp-21478 / adsp-21479 rev. c | page 15 of 76 | july 2013 additional information this data sheet provides a gene ral overview of the adsp-2147x architecture and functionality. for detailed information on the family core architec ture and instruction set, refer to the sharc processor programming reference . related signal chains a signal chain is a series of signal co nditioning electronic com- ponents that receive input (data acquired from sampling either real-time phenomena or from stor ed data) in tandem, with the output of one portion of the ch ain supplying input to the next. signal chains are often used in signal processing applications to gather and process data or to apply system controls based on analysis of real-time phenomena. for more information about this term and related topics, see the signal chain entry in the glossary of ee terms on the analog devices website. analog devices eases signal proc essing system development by providing signal proc essing components that are designed to work together well. a tool for viewing relationships between specific applications and related components is available on the www.analog.com website. the circuits from the lab tm site ( www.analog.com/signal chains ) provides: ? graphical circuit block diag ram presentation of signal chains for a variety of circuit types and applications ? drill down links for components in each chain to selection guides and application information ? reference designs applying be st practice design techniques
rev. c | page 16 of 76 | july 2013 adsp-21477 / adsp-21478 / adsp-21479 pin function descriptions table 11. pin descriptions name type state during/ after reset description addr 23C0 i/o/t (ipu) high-z/driven low (boot) external address. the processor outputs addresses for external memory and peripherals on these pins. the addr pi ns can be multiplexed to support the external memory interface address, flags1 5C8 (i/o) and pwm (o). after reset, all addr pins are in emif mode, and flag(0 C3) pins are in flags mode (default). when configured in the idp_pdap_ctl register, idp channel 0 scans the addr 23C4 pins for parallel input data. data 15C0 i/o/t (ipu) high-z external data. the data pins can be multiplexed to support the external memory interface data (i/o) and flags 7C0 (i/o). ami_ack i (ipu) memory acknowledge. external devices can deassert ami_ack (low) to add wait states to an external memory access. ami_ack is used by i/o devices, memory controllers, or other peripherals to hold off completion of an external memory access. ms 0C1 o/t (ipu) high-z memory select lines 0C1. these lines are asserted (low) as chip selects for the corresponding banks of external memory. the ms 1-0 lines are decoded memory address lines that change at the same time as the other address lines. when no external memory access is occurring the ms 1-0 lines are inactive; they are active however when a conditional memory access instruction is executed, when the condition evaluates as true. the ms1 pin can be used in eport/flash boot mode. for more information on processor booting, see the adsp-214xx sharc processor hardware reference . ami_rd o/t (ipu) high-z ami port read enable. ami_rd is asserted whenever the processor reads a word from external memory. ami_wr o/t (ipu) high-z ami port write enable. ami_wr is asserted when the processor writes a word to external memory. flag0/irq0 i/o (ipu) flag[0] input flag0/interrupt request0. flag1/irq1 i/o (ipu) flag[1] input flag1/interrupt request1. flag2/irq2 /ms2 i/o (ipu) flag[2] input flag2/interrupt request2/memory select2. this pin is multiplexed with ms2 in the 196-ball bga package only. flag3/tmrexp/ms3 i/o (ipu) flag[3] input flag3/timer expired/memory select3. this pin is multiplexed with ms3 in the 196-ball bga package only. the following symbols appear in the type column of table 11: a = asynchronous, i =input, o = output, s = synchronous, a/d = active drive, o/d = open drain, and t = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor. the internal pull-up (ipu) and internal pull-down (ipd) resistors ar e designed to hold the internal path from the pins at the e xpected logic levels. to pull-up or pull-down the external pads to the expect ed logic levels, use external resistors. internal pull-up/pull-d own resistors cannot be enabled/disabled and the value of these resistors cannot be programmed. the ra nge of an ipu resistor can be 26 k to 63 k. the range of an ipd resistor can be 31 k to 85 k. the th ree-state voltage of ipu pads will not reach to full the v dd_ext level; at typical conditions the voltage is in the range of 2.3 v to 2.7 v. in this table, all pins are lvttl compliant with the exception of the thermal diode, shift register, and real-time clock (rtc) pins. not all pins are available in the 88-lead lf csp_vq and 100-lead lqfp package. for more information, see table 2 on page 3 and t able 62 on page 70.
adsp-21477 / adsp-21478 / adsp-21479 rev. c | page 17 of 76 | july 2013 sdras o/t (ipu) high-z/ driven high sdram row address strobe. connect to sdrams ras pin. in conjunction with other sdram command pins, defines the operation for the sdram to perform. sdcas o/t (ipu) high-z/ driven high sdram column address select. connect to sdrams cas pin. in conjunction with other sdram command pins, defines the operation for the sdram to perform. sdwe o/t (ipu) high-z/ driven high sdram write enable. connect to sdrams we or w buffer pin. sdcke o/t (ipu) high-z/ driven high sdram clock enable. connect to sdrams cke pin. enables and disables the clk signal. for details, see the data sheet supplied with the sdram device. sda10 o/t (ipu) high-z/ driven high sdram a10 pin. enables applications to refresh an sdram in parallel with non- sdram accesses. this pin replaces the dsps addr10 pin only during sdram accesses. sddqm o/t (ipu) high-z/ driven high dqm data mask. sdram input mask signal for write accesses and output enable signal for read accesses. input data is masked when dqm is sampled high during a write cycle. the sdram output buffers are placed in a high-z state when dqm is sampled high during a read c ycle. sddqm is driven high from reset de -asser tion until sdram initialization completes. afterwards, it is driven low irrespective of whether any sdram accesses occur or not. sdclk o/t (ipd) high-z/ driving sdram clock output. clock driver for this pin differs from all other clock drivers. see figure 47 on page 65 . for models in the 100-lead package, the sdram interface should be disabled to avoid un necessary power switching by setting the dsdctl bit in sdctl register. for more information, see the adsp-214xx sharc processor hardwa re reference . dai _p 20C1 i/o/t (ipu) high-z digital applications interface . these pins provide the physical interface to the dai sru. the dai sru configuration registers define the combination of on-chip audio-centric peripheral inputs or output s connected to the pin and to the pins output enable. the configuration registers of these peripherals then determines the exact behavior of the pin. any input or output signal present in the dai sru may be routed to any of these pins. dpi _p 14C1 i/o/t (ipu) high-z digital peripheral interface. these pins provide the physical interface to the dpi sru. the dpi sru configuration register s define the combination of on-chip peripheral inputs or outputs connected to the pin and to the pin's output enable. the configuration registers of these peripherals then determine the exact behavior of the pin. any input or output signal present in the dpi sru may be routed to any of these pins. wdt_clkin i watch dog timer clock input. this pin should be pulled low when not used. wdt_clko o watch dog resonator pad output. wdtrsto o (ipu) watch dog timer reset out. table 11. pin descriptions (continued) name type state during/ after reset description the following symbols appear in the type column of table 11: a = asynchronous, i =input, o = output, s = synchronous, a/d = active drive, o/d = open drain, and t = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor. the internal pull-up (ipu) and internal pull-down (ipd) resistors ar e designed to hold the internal path from the pins at the e xpected logic levels. to pull-up or pull-down the external pads to the expect ed logic levels, use external resistors. internal pull-up/pull-d own resistors cannot be enabled/disabled and the value of these resistors cannot be programmed. the ra nge of an ipu resistor can be 26 k to 63 k. the range of an ipd resistor can be 31 k to 85 k. the th ree-state voltage of ipu pads will not reach to full the v dd_ext level; at typical conditions the voltage is in the range of 2.3 v to 2.7 v. in this table, all pins are lvttl compliant with the exception of the thermal diode, shift register, and real-time clock (rtc) pins. not all pins are available in the 88-lead lf csp_vq and 100-lead lqfp package. for more information, see table 2 on page 3 and t able 62 on page 70.
rev. c | page 18 of 76 | july 2013 adsp-21477 / adsp-21478 / adsp-21479 thd_p i thermal diode anode. when not used, this pin can be left floating. thd_m o thermal diode cathode. when not used, this pin can be left floating. mlbclk i media local bus clock. this clock is generated by the mlb controller that is synchronized to the most network and provides the timing for the entire mlb interface at 49.152 mhz at fs = 48 khz. when the mlb controller is not used, this pin should be grounded. mlbdat i/o/t in 3 pin mode. i in 5 pin mode. high-z media local bus data. the mlbdat line is driven by the transmitting mlb device and is received by all other mlb de vices including the mlb controller. the mlbdat line carries the actual data. in 5- pin mlb mode, this pin is an input only. when the mlb controller is not used, this pin should be grounded. mlbsig i/o/t in 3 pin mode. i in 5 pin mode high-z media local bus signal. this is a multiplexed signal which carries the channel/address generated by the mlb controller, as well as the command and rxstatus bytes from mlb devices. in 5-pi n mode, this pin is input only. when the mlb controller is not used, this pin should be grounded. mlbdo o/t high-z media local bus data output (in 5 pin mode). this pin is used only in 5-pin mlb mode and serves as the output data pin. when the mlb controller is not used, this pin should be grounded. mlbso o/t high-z media local bus signal output (in 5 pin mode). this pin is used only in 5-pin mlb mode and serves as the output signal pin. when the mlb controller is not used, this pin should be grounded. sr_sclk i (ipu) shift register serial clock. (active high, rising edge sensitive) sr_clr i (ipu) shift register reset. (active low) sr_sdi i (ipu) shift register serial data input. sr_sdo o (ipu) driven low shift register serial data output. sr_lat i (ipu) shift register latch clock input. (active high, rising edge sensitive) sr_ldo 17C0 o/t (ipu) high-z shift register parallel data output. rtxi i rtc crystal input. if rtc is not used, then this pin needs to be nc (no connect) and the rtc_pdn and rtc_busd is bits of rtc_init register must be set to 1. rtxo o rtc crystal output. if rtc is not used, then this pin needs to be nc (no connect). rtclkout o (ipd) rtc clock output. for calibration purposes. the clock runs at 1 hz. if rtc is not used, then this pin needs to be nc (no connect). table 11. pin descriptions (continued) name type state during/ after reset description the following symbols appear in the type column of table 11: a = asynchronous, i =input, o = output, s = synchronous, a/d = active drive, o/d = open drain, and t = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor. the internal pull-up (ipu) and internal pull-down (ipd) resistors ar e designed to hold the internal path from the pins at the e xpected logic levels. to pull-up or pull-down the external pads to the expect ed logic levels, use external resistors. internal pull-up/pull-d own resistors cannot be enabled/disabled and the value of these resistors cannot be programmed. the ra nge of an ipu resistor can be 26 k to 63 k. the range of an ipd resistor can be 31 k to 85 k. the th ree-state voltage of ipu pads will not reach to full the v dd_ext level; at typical conditions the voltage is in the range of 2.3 v to 2.7 v. in this table, all pins are lvttl compliant with the exception of the thermal diode, shift register, and real-time clock (rtc) pins. not all pins are available in the 88-lead lf csp_vq and 100-lead lqfp package. for more information, see table 2 on page 3 and t able 62 on page 70.
adsp-21477 / adsp-21478 / adsp-21479 rev. c | page 19 of 76 | july 2013 tdi i (ipu) test data input (jtag). provides serial data for the boundary scan logic. tdo o/t high-z test data output (jtag). serial scan output of the boundary scan path. tms i (ipu) test mode select (jtag). used to control the test state machine. tck i test clock (jtag). provides a clock for jtag boundary scan. tck must be asserted (pulsed low) after power-up or held low for proper operation of the device. trst i (ipu) test reset (jtag). resets the test state machine. trst must be asserted (pulsed low) after power-up or held low for proper operation of the processor. emu o (o/d, ipu) high-z emulation status. must be connected to the analog devices dsp tools product line of jtag emulators target board connector only. clk_cfg 1C0 i core to clkin ratio control. these pins set the startup clock frequency. note that the operating frequency can be changed by programming the pll multiplier and divider in the pmctl register at any time after the core comes out of reset. the allowed values are: 00 = 8:1 01 = 32:1 10 = 16:1 11 = reserved clkin i local clock in. used in conjunction with xtal. clkin is the clock input. it configures the processors to use either its internal clock generator or an external clock source. connecting the necessary components to clkin and xtal enables the internal clock generator. connecting the external clock to clkin while leaving xtal unconnected configures the processors to use the external clock source such as an external clock oscillator. clkin may not be halted, changed, or operated below the specified frequency. xtal o crystal oscillator terminal. used in conjunction with clkin to drive an external crystal. reset i processor reset. resets the processor to a known state. upon deassertion, there is a 4096 clkin cycle latency for the pll to lock. after this time, the core begins program execution from the hardware reset vector address. the reset input must be asserted (low) at power-up. resetout /runrstin i/o (ipu) reset out/running reset in. the default setting on this pin is reset out. this pin also has a second function as runrstin which is enabled by setting bit 0 of the runrstctl register. for more information, see the adsp-214xx sharc processor hardware reference . boot_cfg 2C0 i boot configuration select. these pins select the boot mode for the processor. the boot_cfg pins must be valid before reset (hardware and software) is de- asserted. the boot_cfg2 pin is only available on the 196-lead package. table 11. pin descriptions (continued) name type state during/ after reset description the following symbols appear in the type column of table 11: a = asynchronous, i =input, o = output, s = synchronous, a/d = active drive, o/d = open drain, and t = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor. the internal pull-up (ipu) and internal pull-down (ipd) resistors ar e designed to hold the internal path from the pins at the e xpected logic levels. to pull-up or pull-down the external pads to the expect ed logic levels, use external resistors. internal pull-up/pull-d own resistors cannot be enabled/disabled and the value of these resistors cannot be programmed. the ra nge of an ipu resistor can be 26 k to 63 k. the range of an ipd resistor can be 31 k to 85 k. the th ree-state voltage of ipu pads will not reach to full the v dd_ext level; at typical conditions the voltage is in the range of 2.3 v to 2.7 v. in this table, all pins are lvttl compliant with the exception of the thermal diode, shift register, and real-time clock (rtc) pins. not all pins are available in the 88-lead lf csp_vq and 100-lead lqfp package. for more information, see table 2 on page 3 and t able 62 on page 70.
rev. c | page 20 of 76 | july 2013 adsp-21477 / adsp-21478 / adsp-21479 table 12. pin list, power and ground name type description v dd_int p internal power supply. v dd_ext p i/o power supply. v dd_rtc p real-time clock power supply. when rtc is not used, this pin should be connected to v dd_ext . gnd 1 g ground. v dd_thd p thermal diode power supply . when not used, this pin can be left floating. 1 the exposed pad is required to be electric ally and thermally connected to gnd. implem ent this by soldering the exposed pad to a gnd pcb land that is the same size as the exposed pad. the gnd pcb land should be robustly connected to the gnd plane in the pcb for best electrical and thermal performance. see also 88-lfcsp_vq lead assignment on page 68 and 100-lqfp_ep lead assignment on page 70 .
adsp-21477 / adsp-21478 / adsp-21479 rev. c | page 21 of 76 | july 2013 specifications operating conditions 200 mhz 266 mhz 300 mhz parameter 1 1 specifications subject to change without notice. description min nom max min nom max min nom max unit v dd_int internal (core) supply voltage 1.14 1.2 1.26 1.14 1.2 1.26 1.25 1.3 1.35 v v dd_ext external (i/o) supply voltage 3.13 3.3 3.47 3.13 3.3 3.47 3.13 3.3 3.47 v v dd_thd thermal diode supply voltage 3.13 3.3 3.47 3.13 3.3 3.47 3.13 3.3 3.47 v v dd_rtc real-time clock power supply voltage 2.0 3.0 3.6 2.0 3.0 3.6 2.0 3.0 3.6 v v ih 2 2 applies to input and bidirecti onal pins: addr23C0, data15C0, flag3C0, dai_ px, dpi_px, boot_cfgx, clk_cfgx, runrstin , reset , tck, tms, tdi, trst , sda10, ami_ack, mlbclk, mlbdat, mlbsig. high level input voltage @ v dd_ext = max 2.0 2.0 2.0 v v il 3 3 applies to input pin clkin, wdt_clkin. low level input voltage @ v dd_ext = min 0.8 0.8 0.8 v v ih_clkin 3 high level input voltage @ v dd_ext = max 2.2 v dd_ext 2.2 v dd_ext 2.2 v dd_ext v v il_clkin low level input voltage @ v dd_ext = max C0.3 +0.8 C0.3 +0.8 C0.3 +0.8 v t j junction temperature 88-lead lfcsp_vq @ t ambient 0 ? c to +70 ? c 0 105 n/a n/a n/a n/a c t j junction temperature 88-lead lfcsp_vq @ t ambient C40 ? c to +85 ? c C40 +115 n/a n/a n/a n/a c t j 4 4 applies to automotive models only. see automotive products on page 75 . junction temperature 88-lead lfcsp_vq @ t ambient C40 ? c to +105 ? c C40 +125 n/a n/a n/a n/a c t j junction temperature 100-lead lqfp_ep @ t ambient 0c to +70c 0 105 0 105 n/a n/a c t j 4 junction temperature 100-lead lqfp_ep @ t ambient C40c to +85c n/a n/a C40 +125 n/a n/a c t j 4 junction temperature 100-lead lqfp_ep @ t ambient C40c to +105c C40 +125 C40 +125 n/a n/a c t j 5 5 real time clock (rtc) is supported only for products with a tem perature range of 0c to +70c and not supported for all other t emperature grades. for th e status of unused rtc pins please see table 11 on page 16 . junction temperature 196-ball csp_bga @ t ambient 0c to +70c n/a n/a 0 105 0 100 c t j 5 junction temperature 196-ball csp_bga @ t ambient C40c to +85c n/a n/a C40 +125 n/a n/a c
rev. c | page 22 of 76 | july 2013 adsp-21477 / adsp-21478 / adsp-21479 electrical characteristics 200 mhz 266 mhz 300 mhz unit parameter 1 description test conditions min max min max min max v oh 2 high level output voltage @ v dd_ext = min, i oh = C1.0 ma 3 2.4 2.4 2.4 v v ol 2 low level output voltage @ v dd_ext = min, i ol = 1.0 ma 3 0.4 0.4 0.4 v i ih 4, 5 high level input current @ v dd_ext = max, v in = v dd_ext max 10 10 10 a i il 4 low level input current @ v dd_ext = max, v in = 0 v C10 C10 C10 a i ilpu 5 low level input current pull-up @ v dd_ext = max, v in = 0 v 200 200 200 a i ozh 6, 7 three-state leakage current @ v dd_ext = max, v in = v dd_ext max 10 10 10 a i ozl 6 three-state leakage current @ v dd_ext = max, v in = 0 v C10 C10 C10 a i ozlpu 7 three-state leakage current pull-up @ v dd_ext = max, v in = 0 v 200 200 200 a i ozhpd 8 three-state leakage current pull-down @ v dd_ext = max, v in = v dd_ext max 200 200 200 a i dd_rtc v dd_rtc current @ v dd_rtc = 3.0, t j = 25c 0.76 0.76 0.76 a i dd_int 9 supply current (internal) f cclk > 0 mhz table 14 + table 15 asf table 14 + table 15 asf table 14 + table 15 asf ma c in 10, 11 input capacitance t case = 25c 5 5 5 pf 1 specifications subject to change without notice. 2 applies to output and bidirectional pins: addr 23-0, data15-0, ami_rd , ami_wr , flag3C0, dai_px, dpi_px, emu , tdo, resetout ,mlbsig, mlbdat, mlbdo, mlbso, sdras , sdcas , sdwe , sdcke, sda10, sddqm, ms0-1. 3 see output drive currents on page 65 for typical drive current capabilities. 4 applies to input pins: boot_cfgx, clk_cfgx, tck, reset , clkin. 5 applies to input pins with internal pull-ups: trst , tms, tdi. 6 applies to three-statable pins: tdo, mlbdat, mlbsig, mlbdo, and mlbso. 7 applies to three-statable pins with pull-ups: dai_px, dpi_px, emu . 8 applies to three-statable pin with pull-down: sdclk. 9 see engineer-to-engineer note estimatin g power dissipation for ad sp-214xx sharc processors for further information. 10 applies to all signal pins. 11 guaranteed, but not tested.
adsp-21477 / adsp-21478 / adsp-21479 rev. c | page 23 of 76 | july 2013 total power dissipation the information in this section should be augmented with estimating power for adsp-214 xx sharc processors (ee-348) . total power dissipation has two components: 1. internal power consumption is additionally comprised of two components: ? static current due to leakage. table 14 shows the static current consumption (i dd_int_static ) as a function of junction temperature (t j ) and core voltage (v dd_int ). ? dynamic current (i dd_int_dynamic ), due to transistor switching characteristics and activity level of the pro- cessor. the activity level is reflected by the activity scaling factor (asf), which represents the activity level of the application code running on the processor core and having various leve ls of peripheral and exter- nal port activity ( table 13 ). dynamic current consumption is calculated by selecting the asf that corresponds most closely wi th the user application and then multiplying that with the dynamic current consumption ( table 15 ). 2. external power consumption is due to the switching activ- ity of the external pins. table 13. activity scaling factors (asf) 1 activity scaling factor (asf) idle 0.31 low 0.53 medium low 0.62 medium high 0.78 peak-typical (50:50) 2 0.85 peak-typical (60:40) 2 0.93 peak-typical (70:30) 2 1.00 high typical 1.18 high 1.28 peak 1.34 1 see estimating power for adsp-214x x sharc processors (ee-348) for more information on the explanation of the po wer vectors specific to the asf table. 2 ratio of continuous instruction loop (c ore) to sdram control code reads and writes. table 14. static currenti dd_int_static (ma) 1 t j (c) voltage (v dd_int ) 1.05 v 1.10 v 1.15 v 1.20 v 1.25 v 1.30 v 1.35 v C45 < 0.1 < 0.1 0.4 0.8 1.3 2.1 3.3 C35 < 0.1 < 0.1 0.4 0.7 1.1 1.7 2.9 C25 < 0.1 0.2 0.4 0.8 1.2 1.7 2.9 C15 < 0.1 0.4 0.6 1.0 1.4 1.9 3.2 C50.20.60.91.31.82.33.7 +50.50.91.31.82.33.04.4 +15 0.8 1.4 1.8 2.3 3.0 3.7 5.1 +25 1.3 1.9 2.5 3.1 3.9 4.7 6.2 +35 2.0 2.8 3.4 4.2 5.1 6.0 8.0 +45 3.0 3.9 4.7 5.7 6.7 7.8 10.1 +55 4.3 5.4 6.3 7.6 8.8 10.3 12.9 +65 6.0 7.3 8.6 10.1 11.7 13.5 16.4 +75 8.3 9.9 11.5 13.3 15.3 17.4 21.2 +85 11.2 13.2 15.3 17.5 19.9 22.6 27.1 +95 15.2 17.6 20.1 22.9 26.1 29.4 34.6 +100 17.4 20.2 22.9 25.9 29.4 33.0 39.2 +105 20.0 23.0 26.1 29.5 33.4 n/a n/a +115 26.3 30.0 33.9 38.2 42.9 n/a n/a +125 34.4 38.9 43.6 48.8 54.8 n/a n/a 1 valid temperature and voltage ranges are model-specific. see operating conditions on page 21 .
rev. c | page 24 of 76 | july 2013 adsp-21477 / adsp-21478 / adsp-21479 maximum power dissipation see engineer-to-engineer note estimating power dissipation for adsp-2147x sharc processors for detailed thermal and power information regarding ma ximum power dissipation. for information on package thermal specifications, see thermal characteristics on page 66 . package information the information presented in figure 4 provides details about the package branding. for a complete listing of product avail- ability, see ordering guide on page 76 . esd sensitivity absolute maximum ratings stresses greater than those listed in table 17 may cause perma- nent damage to the device. these are stress ratings only; functional operation of the device at these or any other condi- tions greater than those indicated in operating conditions on page 21 is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 15. dynamic current in cclk domaini dd_int_dynamic (ma, with asf = 1.0) 1, 2 f cclk (mhz) voltage (v dd_int ) 1.05 v 1.10 v 1.15 v 1.20 v 1.25 v 1.30 v 1.35 v 10075788286909598 150 111 117 122 128 134 141 146 200 n/a n/a 162 170 178 186 194 266 n/a n/a 215 225 234 246 256 300 n/a n/a n/a n/a 264 279 291 1 the values are not guaranteed as standalone maximum specifications. they must be combin ed with static current per the equations of electrical characteristics on page 22 . 2 valid frequency and voltage ra nges are model-specific. see operating conditions on page 21 . figure 4. typical package brand table 16. package br and information 1 1 nonautomotive only. for branding informati on specific to automotive products, contact analog devices inc. brand key field description t temperature range pp package type z rohs compliant option cc see ordering guide vvvvvv.x assembly lot code n.n silicon revision # rohs compliant designation yyww date code vvvvvv.x n.n tppz-cc s adsp-2147x a #yyww country_of_origin table 17. absolute maximum ratings parameter rating internal (core) supply voltage (v dd_int ) C0.3 v to +1.35 v external (i/o) supply voltage (v dd_ext )C0.3 v to +4.6 v real time clock voltage (v dd_rtc )C0.3 v to +4.6 v thermal diode supply voltage (v dd_thd )C0.3 v to +4.6 v input voltage C0.5 v to +3.8 v output voltage swing C0.5 v to v dd_ext +0.5 v storage temperature range C65c to +150c junction temperature while biased 125c esd (electrostatic discharge) sensitive device. charged devices and circuit boards can discharge without detection. although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy esd. therefore, proper esd precautions should be taken to avoid performance degradation or loss of functionality.
adsp-21477 / adsp-21478 / adsp-21479 rev. c | page 25 of 76 | july 2013 timing specifications use the exact timing information given. do not attempt to derive parameters from the addition or subtraction of others. while addition or su btraction would yield meaningful results for an individual device, the va lues given in this data sheet reflect statistical variations and worst cases. consequently, it is not meaningful to add parameters to derive longer times. see figure 49 on page 65 under test conditions for voltage refer- ence levels. switching characteristics specify how the processor changes its signals. circuitry external to th e processor must be designed for compatibility with these signal characteristics. switching char- acteristics describe what the processor will do in a given circumstance. use switching charac teristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied. timing requirements apply to signals that are controlled by cir- cuitry external to the processor, such as the data input for a read operation. timing requirements guarantee that the processor operates correctly with other devices. core clock requirements the processors internal clock (a multiple of clkin) provides the clock signal for timing inte rnal memory, processor core, and serial ports. during reset, prog ram the ratio between the proces- sors internal clock frequenc y and external (clkin) clock frequency with the clk_cfg1C0 pins. the processors internal clock sw itches at higher frequencies than the system input clock (clk in). to generate the internal clock, the processor uses an internal phase-locked loop (pll, see figure 5 ). this pll-based clocki ng minimizes the skew between the system clock (clkin ) signal and the processors internal clock. voltage controlled oscillator (vco) in application designs, the p ll multiplier value should be selected in such a way that the vco frequency never exceeds f vco specified in table 20 . ? the product of clkin and pllm must never exceed 1/2 of f vco (max) in table 20 if the input divider is not enabled (indiv = 0). ? the product of clkin and pllm must never exceed f vco (max) in table 20 if the input divider is enabled (indiv = 1). the vco frequency is calculated as follows: f vco = 2 pllm f input f cclk = (2 pllm f input ) plld where: f vco = vco output pllm = multiplier value programm ed in the pmctl register. during reset, the pllm value is derived from the ratio selected using the clk_cfg pins in hardware. plld = 2, 4, 8, or 16 based on the divider value programmed on the pmctl register. during reset this value is 2. f input is the input frequency to the pll. f input = clkin when the input divider is disabled, or clkin 2 when the input divider is enabled. note the definitions of the clock periods that are a function of clkin and the appropriate ratio control shown in table 20 . all of the timing specifications for the peripherals are defined in relation to t pclk . see the peripheral specific section for each peripherals timing information. figure 5 shows core to clkin relati onships with an external oscillator or crystal. the shad ed divider/multiplier blocks denote where clock ratios can be set through hardware or soft- ware using the power management control register (pmctl). for more information, see the adsp-214xx sharc processor hardware reference . table 18. clock periods timing requirements description t ck clkin clock period t cclk processor core clock period t pclk peripheral clock period = 2 t cclk t sdclk sdram clock period = (t cclk ) sdckr
rev. c | page 26 of 76 | july 2013 adsp-21477 / adsp-21478 / adsp-21479 figure 5. core clock and system clock relationship to clkin loop filter clkin pclk sdram divider bypass mux pmctl (sdckr) cclk pll xtal clkin divider reset f vco (2 pllm) buf vco buf pmctl (indiv) pll divider resetout clkout (test only)* delay of 4096 clkin cycles pclk pmctl (pllbp) pmctl (plld) f vco f cclk f input *clkout (test only) frequency is the same as f input. this signal is not specified or supported for any design. clk_cfgx/ pmctl (2 pllm) divide by 2 pin mux pmctl (pllbp) cclk resetout coresrst sdclk bypass mux
adsp-21477 / adsp-21478 / adsp-21479 rev. c | page 27 of 76 | july 2013 power-up sequencing the timing requirements for pr ocessor startup are given in table 19 . while no specific power-up sequencing is required between v dd_ext and v dd_int , there are some considerations that the system designs sh ould take into account. ? no power supply should be powered up for an extended period of time (>200 ms) befo re another supply starts to ramp up. ?if the v dd_int power supply comes up after v dd_ext , any pin, such as resetout and reset , may actually drive momentarily until the v dd_int rail has powered up. systems sharing these signals on the bo ard must determine if there are any issues that need to be addressed based on this behavior. note that during power-up, when the v dd_int power supply comes up after v dd_ext , a leakage current of the order of three- state leakage current pull-up, pu ll-down, may be observed on any pin, even if that is an in put only (for example, the reset pin), until the v dd_int rail has powered up. table 19. power-up sequencing timing requirements (processor startup) parameter min max unit timing requirements t rstvdd reset low before v dd_ext or v dd_int on 0 ms t ivddevdd v dd_int on before v dd_ext C200 +200 ms t clkvdd 1 clkin valid after v dd_int and v dd_ext valid 0 200 ms t clkrst clkin valid before reset deasserted 10 2 s t pllrst pll control setup before reset deasserted 20 3 s switching characteristic t corerst core reset deasserted after reset deasserted 4096 t ck + 2 t cclk 4, 5 1 valid v dd_int and v dd_ext assumes that the supplies are fully ramped to their nominal values (it does not matter which supply comes up first). voltage r amp rates can vary from microseconds to hundreds of milliseconds depending on the des ign of the power supply subsystem. 2 assumes a stable clkin signal, after meeting worst-case startup timing of crystal oscillators. refer to your crystal oscillator manufacturer's data sheet for startup time. assume a 25 ms maximum oscillator startup time if using the xtal pin an d internal oscillator circuit in conjunction with an external c rystal. 3 based on clkin cycles. 4 applies after the power-up sequence is complete. subsequent resets require a minimum of four clkin cycles for reset to be held low in order to properly initialize and propagate default states at all i/o pins. 5 the 4096 cycle count depends on t srst specification in table 21 . if setup time is not met, one additional clkin cycle may be added to the core reset time, resulting in 4097 cycles maximum. figure 6. power-up sequencing t rstvdd t clkvdd t clkrst t corerst t pllrst v ddext v ddint clkin clk_cfg1C0 reset resetout t ivddevdd
rev. c | page 28 of 76 | july 2013 adsp-21477 / adsp-21478 / adsp-21479 clock input table 20. clock input parameter 200 mhz 266 mhz 300 mhz unit min max min max min max timing requirements t ck clkin period 40 100 30 1 1 applies only for clkcfg1C0 = 00 and defaul t values for pll control bits in pmctl. 100 26.66 1 100 ns t ckl clkin width low 20 45 15 45 13.33 45 ns t ckh clkin width high 20 45 15 45 13.33 45 ns t ckrf clkin rise/fall (0.4 v to 2.0 v) 3 3 3 ns t cclk 2 2 any changes to pll control bits in the pmctl regis ter must meet core clock timing specification t cclk . cclk period 5 10 3.75 10 3.33 10 ns f vco 3 3 see figure 5 on page 26 for vco diagram. vco frequency 200 600 200 600 200 600 mhz t ckj 4, 5 4 actual input jitter should be combined with ac specifications for acc urate timing analysis. 5 jitter specification is maximum peak-to -peak time interval error (tie) jitter. clkin jitter tolerance C250 +250 C250 +250 C250 +250 ps figure 7. clock input clkin t ck t ckl t ckh t ckj
adsp-21477 / adsp-21478 / adsp-21479 rev. c | page 29 of 76 | july 2013 clock signals the processors can use an external clock or a crystal. see the clkin pin description in table 11 . programs can configure the processor to use its internal cl ock generator by connecting the necessary components to clkin and xtal. figure 8 shows the component connections used for a crystal operating in funda- mental mode. note that the cl ock rate is achieved using a 16.67 mhz crystal and a p ll multiplier ratio 16:1 (cclk:clkin achieves a clock speed of 266 mhz). to achieve the full core clock rate, programs need to configure the multi- plier bits in the pmctl register. reset figure 8. 266 mhz operation (fundamental mode crystal) c 1 2 2pf y1 r1 1m * xtal clkin c2 22pf 16.67 r2 47 * adsp-2147x choose c1 and c2 based on the crystal y1. choose r2 to limit crystal drive power. refer to crystal manufacturer's specifications *typical values table 21. reset parameter min max unit timing requirements t wrst 1 reset pulse width low 4 t ck ns t srst reset setup before clkin low 8 ns 1 applies after the power-up sequence is comp lete. at power-up, the proces sors internal phase-locked l oop requires no more than 1 00 ? s while reset is low, assuming stable v dd and clkin (not including start-up time of external clock oscillator). figure 9. reset clkin reset t srst t wrst
rev. c | page 30 of 76 | july 2013 adsp-21477 / adsp-21478 / adsp-21479 running reset the following timing specification applies to resetout / runrstin pin when it is co nfigured as runrstin . interrupts the following timing specification applies to the flag0, flag1, and flag2 pins when they are config ured as irq0 , irq1 , and irq2 interrupts, as well as the dai_p20C1 and dpi_p14C1 pins when they ar e configured as interrupts. table 22. running reset parameter min max unit timing requirements t wrunrst running reset pulse width low 4 t ck ns t srunrst running reset setup before clkin high 8 ns figure 10. running reset clkin runrstin t wrunrst t srunrst table 23. interrupts parameter min max unit timing requirement t ipw irqx pulse width 2 t pclk + 2 ns figure 11. interrupts interrupt inputs t ipw
adsp-21477 / adsp-21478 / adsp-21479 rev. c | page 31 of 76 | july 2013 core timer the following timing specification applies to flag3 when it is configured as the core timer (tmrexp). timer pwm_out cycle timing the following timing specification applies to timer0 and timer1 in pwm_out (pulse-width modu lation) mode. timer signals are routed to the dpi_p14C1 pi ns through the dpi sru. there- fore, the timing specifications provided below are valid at the dpi_p14C1 pins. table 24. core timer 88-lead lfcsp package all other packages unit parameter min max min max switching characteristic t wctim tmrexp pulse width 4 t pclk C 1.55 4 t pclk C 1.2 ns figure 12. core timer flag3 (tmrexp) t wctim table 25. timer pwm_out timing 88-lead lfcsp package all other packages unit parameter min max min max switching characteristic t pwmo timer pulse width output 2 t pclk C 1.65 2 (2 31 C 1) t pclk 2 t pclk C 1.2 2 (2 31 C 1) t pclk ns figure 13. timer pwm_out timing pwm outputs t pwmo
rev. c | page 32 of 76 | july 2013 adsp-21477 / adsp-21478 / adsp-21479 timer wdth_cap timing the following timing specification applies to timer0 and timer1, and in wdth_cap (pulse widt h count and capture) mode. timer signals are routed to the dpi_p14C1 pins through the sru. therefore, the timing specification provided below is valid at the dpi_p14C1 pins. watchdog timer timing table 26. timer width capture timing parameter min max unit timing requirement t pwi timer pulse width 2 t pclk 2 (2 31 C 1) t pclk ns figure 14. timer width capture timing timer capture inputs t pwi table 27. watchdog timer timing parameter min max unit timing requirement t wdtclkper 100 1000 ns switching characteristics t rst wdt clock rising edge to watchdog timer reset falling edge 37.6 ns t rstpw reset pulse width 64 t wdtclkper 1 ns 1 when the internal oscillator is used, the 1/t wdtclkper varies from 1.5 mhz to 2.5 mhz and the wdt_clkin pin should be pulled low. figure 15. watchdog timer timing wdt_clkin wdtrsto t wdtclkper t rst t rstpw
adsp-21477 / adsp-21478 / adsp-21479 rev. c | page 33 of 76 | july 2013 pin to pin direct routing (dai and dpi) for direct pin connections only (for example, dai_pb01_i to dai_pb02_o). table 28. dai/dpi pin to pin routing parameter min max unit timing requirement t dpio delay dai/dpi pin input valid to dai/dpi output valid 1.5 10 ns figure 16. dai pin to pin direct routing dai_pn dpi_pn dai_pm dpi_pm t dpio
rev. c | page 34 of 76 | july 2013 adsp-21477 / adsp-21478 / adsp-21479 precision clock generator (direct pin routing) this timing is only valid when the sru is configured such that the precision clock generator (pcg) takes its inputs directly from the dai pins (via pin buffers) and sends its outputs directly to the dai pins. for the other ca ses, where the pcgs inputs and outputs are not directly routed to/from dai pins (via pin buffers) there is no timing data available. all timing param- eters and switching characteristics apply to external dai pins (dai_p01 C dai_p20). table 29. precision clock generator (direct pin routing) 88-lead lfcsp package all other packages unit parameter min max min max timing requirement s t pcgip input clock period t pclk 4 t pclk 4 ns t strig pcg trigger setup before falling edge of pcg input clock 4.5 4.5 ns t htrig pcg trigger hold after falling edge of pcg input clock 33ns switching characteristics t dpcgio pcg output clock and frame sync active edge delay after pcg input clock 2.5 2 t pclk 2.5 12.5 ns t dtrigclk pcg output clock delay after pcg trigger 2.5 + (2.5 t pcgip )2 t pclk + (2.5 t pcgip ) 2.5 + (2.5 t pcgip ) 12.5 + (2.5 t pcgip )ns t dtrigfs pcg frame sync delay after pcg trigger 2.5 + ((2.5 + d C ph) t pcgip ) 2 t pclk + ((2.5 + d C ph) t pcgip ) 2.5 + ((2.5 + d C ph) t pcgip ) 12.5 + ((2.5 + d C ph) t pcgip ) ns t pcgow 1 output clock period 2 t pcgip C 1 2 t pcgip C 1 ns d = fsxdiv, ph = fsxphase. for more information, see the adsp-214xx sharc processor hardware reference, precision clock genera tors chapter. 1 normal mode of operation. figure 17. precision clock generator (direct pin routing) dai_pn dpi_pn pcg_trigx_i dai_pm dpi_pm pcg_extx_i (clkin) dai_py dpi_py pck_clkx_o dai_pz dpi_pz pcg_fsx_o t dtrigfs t dtrigclk t dpcgio t strig t htrig t pcgow t dpcgio t pcgip
adsp-21477 / adsp-21478 / adsp-21479 rev. c | page 35 of 76 | july 2013 flags the timing specifications provided below apply to addr23C0 and data7C0 when config ured as flags. see table 11 on page 16 for more information on flag use. table 30. flags parameter min max unit timing requirement t fipw flags in pulse width 1 2 t pclk + 3 ns switching characteristic t fopw flags out pulse width 1 2 t pclk C 3.5 ns 1 this is applicable when the flags are connected to dpi_p14C1, addr23C0, data7C0 and flag3C0 pins. figure 18. flags flag inputs flag outputs t fopw t fipw
rev. c | page 36 of 76 | july 2013 adsp-21477 / adsp-21478 / adsp-21479 sdram interface timing table 31. sdram interface timing 133 mhz 150 mhz unit parameter min max min max timing requirement s t ssdat data setup before sdclk 0.7 0.7 ns t hsdat data hold after sdclk 1.66 1.5 ns switching characteristic s t sdclk 1 1 systems should use the sdram model with a speed grade higher than the desired sdram controller speed. for example, to run the s dram controller at 133 mhz the sdram model with a speed grade of 143 mhz or above should be used. see engineer-t o-engineer note interfacing sdram memory to s harc processors (ee-286) for more information on hardware design guidelines for the sdram interface. sdclk period 7.5 6.66 ns t sdclkh sdclk width high 2.5 2.2 ns t sdclkl sdclk width low 2.5 2.2 ns t dcad 2 2 command pins include: sdcas , sdras , sdwe , msx , sda10, sdqm, sdcke. command, addr, data de lay after sdclk 5 4.75 ns t hcad 2 command, addr, data hold after sdclk 1 1 ns t dsdat data disable after sdclk 6.2 5.3 ns t ensdat data enable after sdclk 0.3 0.3 ns figure 19. sdram interface timing sdclk data (in) data (out) command/addr (out) t sdclkh t sdclkl t hsdat t ssdat t hcad t dcad t ensdat t dcad t dsdat t hcad t sdclk
adsp-21477 / adsp-21478 / adsp-21479 rev. c | page 37 of 76 | july 2013 ami read use these specifications for asyn chronous interfacing to memo- ries. note that timing for ami_ack, addr, data, ami_rd , ami_wr , and strobe timing parameters only apply to asyn- chronous access mode. table 32. ami read parameter min max unit timing requirements t dad 1, 2, 3 address selects delay to data valid w + t sdclk C 6.32 ns t drld 1, 3 ami_rd low to data valid w C 3 ns t sds 4, 5 data setup to ami_rd high 2.6 ns t hdrh data hold from ami_rd high 0.4 ns t daak 2, 6 ami_ack delay from address selects t sdclk C 10 + w ns t dsak 4 ami_ack delay from ami_rd low w C 7.0 ns switching characteristics t drha address selects hold after ami_rd high rhc + 0.38 ns t darl 2 address selects to ami_rd low t sdclk C 5 ns t rw ami_rd pulse width w C 1.4 ns t rwr ami_rd high to ami_rd low hi + t sdclk C 1.2 ns w = (number of wait states specified in amictlx register) t sdclk . rhc = (number of read hold cycles specified in amictlx register) t sdclk where predis = 0 hi = rhc: read to read from same bank hi = rhc + ic: read to read from different bank hi = rhc + max (ic, (4 t sdclk )) : read to write from same or different bank where predis = 1 hi = rhc + max (ic, (4 t sdclk )) : read to write from same or different bank hi = rhc + (3 t sdclk ): read to read from same bank hi = rhc + max (ic, (3 t sdclk )) : read to read from different bank ic = (number of idle cycles sp ecified in amictlx register) t sdclk h = (number of hold cycles specified in amictlx register) t sdclk . 1 data delay/setup: system must meet t dad , t drld , or t sds. 2 the falling edge of ami_ms x, is referenced. 3 the maximum limit of timing requirement values for t dad and t drld parameters are applicable for the case where ami_ack is always high and when the ack feature is not used. 4 note that timing for ami_ack, addr, data, ami_rd , ami_wr , and strobe timing parameters only apply to asynchronous access mode. 5 data hold: user must meet t hdrh in asynchronous access mode. see test conditions on page 65 for the calculation of hold times given capacitive and dc loads. 6 ami_ack delay/setup: user must meet t daak , or t dsak , for deassertion of ami_ack (low).
rev. c | page 38 of 76 | july 2013 adsp-21477 / adsp-21478 / adsp-21479 figure 20. ami read ack data t drha t rw t hdrh t rwr t dad t darl t drld t sds t dsak t daak wr rd addr msx
adsp-21477 / adsp-21478 / adsp-21479 rev. c | page 39 of 76 | july 2013 ami write use these specifications for asyn chronous interfacing to memo- ries. note that timing for ami_ack, addr, data, ami_rd , ami_wr , and strobe timing parameters only apply to asyn- chronous access mode. table 33. ami write parameter min max unit timing requirements t daak ami_ack delay from address selects 1, 2 t sdclk C 10.1 + w ns t dsak ami_ack delay from ami_wr low 1, 3 w C 7.1 ns switching characteristics t dawh address selects to ami_wr deasserted 2 t sdclk C4.4 + w ns t dawl address selects to ami_wr low 2 t sdclk C 4.5 ns t ww ami_wr pulse width w C 1.3 ns t ddwh data setup before ami_wr high t sdclk C 4.3 + w ns t dwha address hold after ami_wr deasserted h ns t dwhd data hold after ami_wr deasserted h ns t datrwh data disable after ami_wr deasserted 4 t sdclk C 1.37 + h t sdclk + 6.75+ h ns t wwr ami_wr high to ami_wr low 5 t sdclk C 1.5+ h ns t ddwr data disable before ami_rd low 2 t sdclk C 7.1 ns t wde ami_wr low to data enabled t sdclk C 4.5 ns w = (number of wait states specified in amictlx register) t sdclk h = (number of hold cycles specified in amictlx register) t sdclk 1 ami_ack delay/setup: system must meet t daak , or t dsak , for deassertion of ami_ack (low). 2 the falling edge of ami_msx is referenced. 3 note that timing for ami_ack, addr, data, ami_rd , ami_wr , and strobe timing parameters only applies to asynchronous access mode. 4 see test conditions on page 65 for calculation of hold times given capacitive and dc loads. 5 for write to write: t sdclk + h, for both same bank and diff erent bank. for write to read: 3 t sdclk + h, for the same bank and different banks.
rev. c | page 40 of 76 | july 2013 adsp-21477 / adsp-21478 / adsp-21479 figure 21. ami write ack data t dawh t dwha t wwr t datrwh t dwhd t ww t ddwr t ddwh t dawl t wde t dsak t daak rd wr addr msx
adsp-21477 / adsp-21478 / adsp-21479 rev. c | page 41 of 76 | july 2013 serial ports in slave transmitter mode and master receiver mode, the maxi- mum serial port frequency is f pclk /8. in master transmitter mode and slave receiver mode, the maximum serial port clock frequency is f pclk /4. to determine whether communication is possible between two devices at clock speed, n, the fo llowing specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) sclk width. serial port signals (sclk, fs, data channel a, data channel b) are routed to the dai_p20C1 pins using the sru. therefore, the timing specifications provided below are valid at the dai_p20C1 pins. table 34. serial portsexternal clock 88-lead lfcsp package all other packages unit parameter min max min max timing requirements t sfse 1 frame sync setup before sclk (externally generated frame sync in either transmit or receive mode) 42.5ns t hfse 1 frame sync hold after sclk (externally generated frame sync in either transmit or receive mode) 42.5ns t sdre 1 receive data setup before receive sclk 4 2.5 ns t hdre 1 receive data hold after sclk 4 2.5 ns t sclkw sclk width (t pclk 4) 2 C 1.5 (t pclk 4) 2 C 1.5 ns t sclk sclk period t pclk 4 t pclk 4 ns switching characteristics t dfse 2 frame sync delay after sclk (internally generated frame sync in either transmit or receive mode) 15 15 ns t hofse 2 frame sync hold after sclk (internally generated frame sync in either transmit or receive mode) 22ns t ddte 2 transmit data delay after transmit sclk 15 15 ns t hdte 2 transmit data hold after transmit sclk 2 2 ns 1 referenced to sample edge. 2 referenced to drive edge.
rev. c | page 42 of 76 | july 2013 adsp-21477 / adsp-21478 / adsp-21479 table 35. serial portsinternal clock 88-lead lfcsp package all other packages unit parameter min max min max timing requirements t sfsi 1 frame sync setup before sclk (externally generated frame sync in either transmit or receive mode) 13 10.5 ns t hfsi 1 frame sync hold after sclk (externally generated frame sync in either transmit or receive mode) 2.5 2.5 ns t sdri 1 receive data setup before sclk 13 10.5 ns t hdri 1 receive data hold after sclk 2.5 2.5 ns switching characteristics t dfsi 2 frame sync delay after sclk (internally generated frame sync in transmit mode) 55ns t hofsi 2 frame sync hold after sclk (internally generated frame sync in transmit mode) C1.0 C1.0 ns t dfsir 2 frame sync delay after sclk (internally generated frame sync in receive mode) 10.7 10.7 ns t hofsir 2 frame sync hold after sclk (internally generated frame sync in receive mode) C1.0 C1.0 ns t ddti 2 transmit data delay after sclk 4 4 ns t hdti 2 transmit data hold after sclk C1.0 C1.0 ns t sckliw transmit or receive sclk width 2 t pclk C 1.5 2 t pclk + 1.5 2 t pclk C 1.5 2 t pclk + 1.5 ns 1 referenced to the sample edge. 2 referenced to drive edge.
adsp-21477 / adsp-21478 / adsp-21479 rev. c | page 43 of 76 | july 2013 figure 22. serial ports drive edge sample edge dai_p20C1 (data channel a/b) dai_p20C1 (fs) dai_p20C1 (sclk) t hofsir t hfsi t hdri data receiveinternal clock drive edge sample edge dai_p20C1 (data channel a/b) dai_p20C1 (fs) dai_p20C1 (sclk) t hfsi t ddti data transmitinternal clock drive edge sample edge dai_p20C1 (data channel a/b) dai_p20C1 (fs) dai_p20C1 (sclk) t hofse t hofsi t hdti t hfse t hdte t ddte data transmitexternal clock drive edge sample edge dai_p20C1 (data channel a/b) dai_p20C1 (fs) dai_p20C1 (sclk) t hofse t hfse t hdre data receiveexternal clock t sclkiw t dfsir t sfsi t sdri t sclkw t dfse t sfse t sdre t dfse t sfse t sfsi t dfsi t sclkiw t sclkw
rev. c | page 44 of 76 | july 2013 adsp-21477 / adsp-21478 / adsp-21479 table 36. serial portsexternal late frame sync 88-lead lfcsp package all other packages unit parameter min max min max switching characteristics t ddtlfse 1 data delay from late extern al transmit frame sync or external receive frame sync with mce = 1, mfd = 0 2 t pclk 13.5 ns t ddtenfs 1 data enable for mce = 1, mfd = 0 0.5 0.5 ns 1 the t ddtlfse and t ddtenfs parameters apply to left-jus tified as well as dsp serial mode, and mce = 1, mfd = 0. figure 23. external late frame sync 1 1 this figure reflects changes made to support left -justified mode. drive sample external receive fs with mce = 1, mfd = 0 2nd bit dai_p20C1 (sclk) dai_p20C1 (fs) dai_p20C1 (data channel a/b) 1st bit drive t ddte/i t hdte/i t ddtlfse t ddtenfs t sfse/i drive sample late external transmit fs 2nd bit dai_p20C1 (sclk) dai_p20C1 (fs) dai_p20C1 (data channel a/b) 1st bit drive t ddte/i t hdte/i t ddtlfse t ddtenfs t sfse/i t hfse/i t hfse/i
adsp-21477 / adsp-21478 / adsp-21479 rev. c | page 45 of 76 | july 2013 table 37. serial portsenable and three-state 88-lead lfcsp package all other packages unit parameter min max min max switching characteristics t ddten 1 data enable from external transmit sclk 2 2 ns t ddtte 1 data disable from external transmit sclk 23 20 ns t ddtin 1 data enable from internal transmit sclk C1 C1 ns 1 referenced to drive edge. figure 24. enable and three-state drive edge drive edge drive edge t ddtin t ddten t ddtte dai_p20C1 (sclk, int) dai_p20C1 (data channel a/b) dai_p20C1 (sclk, ext) dai_p20C1 (data channel a/b)
rev. c | page 46 of 76 | july 2013 adsp-21477 / adsp-21478 / adsp-21479 the sportx_tdv_o output sign al (routing unit) becomes active in sport multichannel/packed mode. during transmit slots (enabled with active ch annel selection registers), the sportx_tdv_o is asserted for communication with external devices. table 38. serial portstd v (transmit data valid) 88-lead lfcsp package all other packages unit parameter min max min max switching characteristics 1 t drdven tdv assertion delay from drive edge of external clock 3 3 ns t dfdven tdv deassertion delay from drive edge of external clock 2 t pclk 13.25 ns t drdvin tdv assertion delay from drive ed ge of internal clock C0.1 C0.1 ns t dfdvin tdv deassertion delay from drive edge of internal clock 3.5 3.5 ns 1 referenced to drive edge. figure 25. serial portstdv internal and external clock drive edge drive edge dai_p20C1 (sclk, ext) t drdven t dfdven drive edge drive edge dai_p20C1 (sclk, int) t drdvin t dfdvin tdvx dai_p20-1 tdvx dai_p20-1
adsp-21477 / adsp-21478 / adsp-21479 rev. c | page 47 of 76 | july 2013 input data port (idp) the timing requirements for the idp are given in table 39 . idp signals are routed to the dai_p20C1 pins using the sru. there- fore, the timing specifications provided below are valid at the dai_p20C1 pins. table 39. input data port (idp) 88-lead lfcsp package all other packages unit parameter min max min max timing requirements t sisfs 1 frame sync setup before serial clock rising edge 4.5 3.8 ns t sihfs 1 frame sync hold after serial clock rising edge 3 2.5 ns t sisd 1 data setup before serial clock rising edge 4 2.5 ns t sihd 1 data hold after serial clock rising edge 3 2.5 ns t idpclkw clock width (t pclk 4) 2 C 1 (t pclk 4) 2 C 1 ns t idpclk clock period t pclk 4 t pclk 4 ns 1 the serial clock, data, and frame sync signals can come from any of the dai pins. the serial clock and frame sync signals can also come via pcg or sports. the pcgs input can be either clkin or any of the dai pins. figure 26. idp master timing dai_p20C1 (sclk) sample edge dai_p20C1 (fs) dai_p20C1 (sdata) t ipdclk t ipdclkw t sisfs t sihfs t sihd t sisd
rev. c | page 48 of 76 | july 2013 adsp-21477 / adsp-21478 / adsp-21479 parallel data acquisition port (pdap) the timing requirements for the pdap are provided in table 40 . pdap is the parallel mode operation of channel 0 of the idp. for details on the operation of the pdap, see the pdap chapter of the adsp-214xx sharc pr ocessor hardware reference . note that the 20 bits of external pdap data can be provided through the addr23C0 pins or over the dai pins. table 40. parallel data acquisition port (pdap) 88-lead lfcsp package all other packages unit parameter min max min max timing requirements t sphold 1 pdap_hold setup before pdap_clk sample edge 4 2.5 ns t hphold 1 pdap_hold hold after pdap_clk sample edge 4 2.5 ns t pdsd 1 pdap_dat setup before sclk pdap_clk sample edge 5 3.85 ns t pdhd 1 pdap_dat hold after sclk pdap_clk sample edge 4 2.5 ns t pdclkw clock width (t pclk 4) 2 C 3 (t pclk 4) 2 C 3 ns t pdclk clock period t pclk 4 t pclk 4 ns switching characteristics t pdhldd delay of pdap strobe after last pdap_clk capture edge for a word 2 t pclk + 3 2 t pclk + 3 ns t pdstrb pdap strobe pulse width 2 t pclk C 1.5 2 t pclk C 1.5 ns 1 source pins of data and control are addr23C0 or dai pins. source pins for sclk and fs are: 1) da i pins, 2) clkin through pcg, or 3) dai pins through pcg. figure 27. pdap timing dai_p20C1 (pdap_clk) sample edge dai_p20C1 (pdap_hold) dai_p20C1 (pdap_strobe) t pdstrb t pdhldd t pdhd t pdsd t sphold t hphold t pdclk t pdclkw dai_p20C1/ addr23C4 (pdap_data)
adsp-21477 / adsp-21478 / adsp-21479 rev. c | page 49 of 76 | july 2013 sample rate converterserial input port the asrc input signals are rout ed from the dai_p20C1 pins using the sru. therefore, the timi ng specifications provided in table 41 are valid at the dai_p20C1 pins. table 41. asrc, serial input port parameter min max unit timing requirements t srcsfs 1 frame sync setup before serial clock rising edge 4 ns t srchfs 1 frame sync hold after serial clock rising edge 5.5 ns t srcsd 1 data setup before serial clock rising edge 4 ns t srchd 1 data hold after serial clock rising edge 5.5 ns t srcclkw clock width (t pclk 4) 2 C 1 ns t srcclk clock period t pclk 4 ns 1 the serial clock, data, and frame sync signals can come from any of the dai pins. the serial clock and frame sync signals can also come via pcg or sports. pcgs input can be either clkin or any of the dai pins. figure 28. asrc serial input port timing dai_p20C1 (sclk) sample edge dai_p20C1 (fs) dai_p20C1 (sdata) t srcclk t srcclkw t srcsfs t srchfs t srchd t srcsd
rev. c | page 50 of 76 | july 2013 adsp-21477 / adsp-21478 / adsp-21479 sample rate converterserial output port for the serial output port, the frame sync is an input, and it should meet setup and hold times with regard to the serial clock on the output port. the serial da ta output has a hold time and delay specification with regard to serial clock. note that serial clock rising edge is the sampling edge and the falling edge is the drive edge. table 42. asrc, serial output port 88-lead lfcsp package all other packages unit parameter min max min max timing requirements t srcsfs 1 frame sync setup before serial clock rising edge 4 4 ns t srchfs 1 frame sync hold after serial clock rising edge 5.5 5.5 ns t srcclkw clock width (t pclk 4) 2 C 1 (t pclk 4) 2 C 1 ns t srcclk clock period t pclk 4 t pclk 4 ns switching characteristics t srctdd 1 transmit data delay after serial clock falling edge 2 t pclk 13 ns t srctdh 1 transmit data hold after serial clock falling edge 1 1 ns 1 the serial clock, data, and frame sync signals can come from any of the dai pins. the serial clock and frame sync signals can also come via pcg or sports. pcgs input can be either clkin or any of the dai pins. figure 29. asrc serial output port timing dai_p20C1 (sclk) sample edge dai_p20C1 (fs) dai_p20C1 (sdata) t srcclk t srcclkw t srcsfs t srchfs t srctdd t srctdh
adsp-21477 / adsp-21478 / adsp-21479 rev. c | page 51 of 76 | july 2013 pulse-width modulation generators (pwm) the following timing specifications apply when the addr23C8/dpi_14C1 pins are configured as pwm. table 43. pulse-width modulation (pwm) timing 88-lead lfcsp package all other packages unit parameter min max min max switching characteristics t pwmw pwm output pulse width t pclk C 2 (2 16 C 2) t pclk t pclk C 2 (2 16 C 2) t pclk ns t pwmp pwm output period 2 t pclk C 2 (2 16 C 1) t pclk 2 t pclk C 1.5 (2 16 C 1) t pclk ns figure 30. pwm timing pwm outputs t pwmw t pwmp
rev. c | page 52 of 76 | july 2013 adsp-21477 / adsp-21478 / adsp-21479 s/pdif transmitter serial data input to the s/pdif transmitter can be formatted as left-justified, i 2 s, or right-justified with word widths of 16, 18, 20, or 24 bits. the following se ctions provide timing for the transmitter. s/pdif transmitter-serial input waveforms figure 31 shows the right-justified mo de. frame sync is high for the left channel and low for the ri ght channel. data is valid on the rising edge of serial clock. the msb is delayed the minimum in 24-bit output mode or the maximum in 16-bit output mode from a frame sync transition, so that when there are 64 serial clock periods per frame sync period, the lsb of the data is right- justified to the next frame sync transition. figure 32 shows the default i 2 s-justified mode. the frame sync is low for the left channel and high for the right channel. data is valid on the rising edge of serial clock. the msb is left-justified to the frame sync transition but with a delay. figure 33 shows the left-justified mo de. the frame sync is high for the left channel a nd low for the right channel. data is valid on the rising edge of serial clock. the msb is left-justified to the frame sync transition with no delay. table 44. s/pdif transmitter right-justified mode parameter nominal unit timing requirement t rjd fs to msb delay in right-justified mode 16-bit word mode 18-bit word mode 20-bit word mode 24-bit word mode 16 14 12 8 sclk sclk sclk sclk figure 31. right-justified mode table 45. s/pdif transmitter i 2 s mode parameter nominal unit timing requirement t i2sd fs to msb delay in i 2 s mode 1 sclk figure 32. i 2 s-justified mode msb left/right channel lsb lsb msbC1 msbC2 lsb+2 lsb+1 dai_p20C1 fs dai_p20C1 sclk dai_p20C1 sdata t rjd msb left/right channel lsb msbC1 msbC2 lsb+2 lsb+1 dai_p20C1 fs dai_p20C1 sclk dai_p20C1 sdata t i2sd
adsp-21477 / adsp-21478 / adsp-21479 rev. c | page 53 of 76 | july 2013 table 46. s/pdif transmitter left-justified mode parameter nominal unit timing requirement t ljd fs to msb delay in left-justified mode 0 sclk figure 33. left-justified mode msb left/right channel lsb msbC1 msbC2 lsb+2 lsb+1 dai_p20C1 fs dai_p20C1 sclk dai_p20C1 sdata t ljd
rev. c | page 54 of 76 | july 2013 adsp-21477 / adsp-21478 / adsp-21479 s/pdif transmitter input data timing the timing requirements for th e s/pdif transmitter are given in table 47 . input signals are routed to the dai_p20C1 pins using the sru. therefore, the ti ming specifications provided below are valid at the dai_p20C1 pins. oversampling clock (txclk) switching characteristics the s/pdif transmitter requires an oversampling clock input. this high frequency clock (txclk) input is divided down to generate the internal biphase clock. table 47. s/pdif transmitter input data timing 88-lead lfcsp package all other packages unit parameter min max min max timing requirements t sisfs 1 frame sync setup before serial clock rising edge 4.5 3 ns t sihfs 1 frame sync hold after serial clock rising edge 3 3 ns t sisd 1 data setup before serial clock rising edge 4.5 3 ns t sihd 1 data hold after serial clock rising edge 3 3 ns t sitxclkw transmit clock width 9 9 ns t sitxclk transmit clock period 20 20 ns t sisclkw clock width 36 36 ns t sisclk clock period 80 80 ns 1 the serial clock, data, and frame sync signals can come from any of the dai pins. the serial clock and frame sync signals can also come via pcg or sports. pcgs input can be either clkin or any of the dai pins. figure 34. s/pdif transmitter input timing sample edge dai_p20C1 (txclk) dai_p20C1 (sclk) dai_p20C1 (fs) dai_p20C1 (sdata) t sitxclkw t sitxclk t sisclkw t sisclk t sisfs t sihfs t sisd t sihd table 48. oversampling clock (txc lk) switching characteristics parameter max unit frequency for txclk = 384 frame sync o versampling ratio frame sync 1/t sitxclk mhz frequency for txclk = 256 frame sync 49.2 mhz frame rate (fs) 192.0 khz
adsp-21477 / adsp-21478 / adsp-21479 rev. c | page 55 of 76 | july 2013 s/pdif receiver the following section describes timing as it relates to the s/pdif receiver. internal digital pll mode in the internal digital phase-lock ed loop mode the internal pll (digital pll) generates the 512 fs clock. table 49. s/pdif receiver inte rnal digital pll mode timing parameter min max unit switching characteristics t dfsi fs delay after serial clock 5 ns t hofsi fs hold after serial clock C2 ns t ddti transmit data delay after serial clock 5 ns t hdti transmit data hold after serial clock C2 ns t sclkiw 1 transmit serial clock width 38.5 ns 1 the serial clock frequency is 64 frame s ync (fs) where fs = the frequency of lrclk. figure 35. s/pdif receiver internal digital pll mode timing dai_p20C1 (sclk) sample edge dai_p20C1 (fs) dai_p20C1 (data channel a/b) drive edge t sclkiw t dfsi t hofsi t ddti t hdti
rev. c | page 56 of 76 | july 2013 adsp-21477 / adsp-21478 / adsp-21479 spi interfacemaster both the primary and secondary spis are available through dpi only. the timing provided in table 50 and table 51 applies to both. table 50. spi interface protocolmaster switching and timing specifications 88-lead lfcsp package all other packages unit parameter min max min max timing requirements t sspidm data input valid to spiclk edge (data input setup time) 10 8.6 ns t hspidm spiclk last sampling edge to data input not valid 2 2 ns switching characteristics t spiclkm serial clock cycle 8 t pclk C 2 8 t pclk C 2 ns t spichm serial clock high period 4 t pclk C 2 4 t pclk C 2 ns t spiclm serial clock low period 4 t pclk C 2 4 t pclk C 2 ns t ddspidm spiclk edge to data out valid (data out delay time) 2.5 2.5 t hdspidm spiclk edge to data out not valid (data out hold time) 4 t pclk C 2 4 t pclk C 2 ns t sdscim dpi pin (spi device select) low to first spiclk edge 4 t pclk C 2 4 t pclk C 2 ns t hdsm last spiclk edge to dpi pin (spi device select) high 4 t pclk C 2 4 t pclk C 2 ns t spitdm sequential transfer delay 4 t pclk C 2 4 t pclk C 1.4 ns figure 36. spi master timing t spichm t sdscim t spiclm t spiclkm t hdsm t spitdm t ddspidm t hspidm t sspidm dpi (output) mosi (output) miso (input) mosi (output) miso (input) cphase = 1 cphase = 0 t hdspidm t hspidm t hspidm t sspidm t sspidm t ddspidm t hdspidm spiclk (cp = 0, cp = 1) (output)
adsp-21477 / adsp-21478 / adsp-21479 rev. c | page 57 of 76 | july 2013 spi interfaceslave table 51. spi interface protocolslave switching and timing specifications 88-lead lfcsp package all other packages unit parameter min max min max timing requirements t spiclks serial clock cycle 4 t pclk C 2 4 t pclk C 2 ns t spichs serial clock high period 2 t pclk C 2 2 t pclk C 2 ns t spicls serial clock low period 2 t pclk C 2 2 t pclk C 2 ns t sdsco spids assertion to first spiclk edge, cphase = 0 or cphase = 1 2 t pclk 2 t pclk ns t hds last spiclk edge to spids not asserted, cphase = 0 2 t pclk 2 t pclk ns t sspids data input valid to spiclk edge (data input setup time) 2 2 ns t hspids spiclk last sampling edge to data input not valid 2 2 ns t sdppw spids deassertion pulse width (cphase = 0) 2 t pclk 2 t pclk ns switching characteristics t dsoe spids assertion to data out active 0 13 0 10.25 ns t dsoe 1 spids assertion to data out active (spi2) 0 13 0 10.25 ns t dsdhi spids deassertion to data high impedance 0 2 t pclk 013.25 ns t dsdhi 1 spids deassertion to data high impedance (spi2) 0 2 t pclk 013.25 ns t ddspids spiclk edge to data out vali d (data out delay time) 13 11.5 ns t hdspids spiclk edge to data out not valid (data out hold time) 2 t pclk 2 t pclk ns t dsov spids assertion to data out valid (cphase = 0) 5 t pclk 5 t pclk ns 1 the timing for these parameters a pplies when the spi is routed through the signal routing unit. for more information, see the p rocessor hardware refere nce, serial peripheral interface port (spi) chapter. figure 37. spi slave timing t spichs t spicls t spiclks t hds t sdppw t sdsco t dsoe t ddspids t ddspids t dsdhi t hdspids t hspids t sspids t dsdhi t dsov t hspids t hdspids spids (input) miso (output) mosi (input) miso (output) mosi (input) cphase = 1 cphase = 0 spiclk (cp = 0, cp = 1) (input) t sspids
rev. c | page 58 of 76 | july 2013 adsp-21477 / adsp-21478 / adsp-21479 media local bus all the numbers given are appl icable for all speed modes (1024 fs, 512 fs, and 256 fs for 3-pin; 512 fs and 256 fs for 5-pin) unless otherwise specified. please refer to medialb speci- fication document rev 3.0 for more details. table 52. mlb interface, 3-pin specifications parameter min typ max unit 3-pin characteristics t mlbclk mlb clock period 1024 fs 512 fs 256 fs 20.3 40 81 ns ns ns t mckl mlbclk low time 1024 fs 512 fs 256 fs 6.1 14 30 ns ns ns t mckh mlbclk high time 1024 fs 512 fs 256 fs 9.3 14 30 ns ns ns t mckr mlbclk rise time (v il to v ih ) 1024 fs 512 fs/256 fs 1 3 ns ns t mckf mlbclk fall time (v ih to v il ) 1024 fs 512 fs/256 fs 1 3 ns ns t mpwv 1 mlbclk pulse width variation 1024 fs 512 fs/256 0.7 2.0 ns p-p ns p-p t dsmcf dat/sig input setup time 1 ns t dhmcf dat/sig input hold time 1.2 ns t mcfdz dat/sig output time to three-state 0 15 ns t mcdrv dat/sig output data delay from mlbclk rising edge 8 ns t mdzh 2 bus hold time 1024 fs 512 fs/256 2 4 ns ns c mlb dat/sig pin load 1024 fs 512 fs/256 40 60 pf pf 1 pulse width variation is measured at 1.25 v by triggering on one edge of mlbclk and measuring the spread on the other edge, mea sured in ns peak -to-peak (p-p). 2 the board must be designed to ensure that the high impedance bus does not leave the lo gic state of the final driven bit for thi s time period. therefore, coupling must be minimized while meeting the ma ximum capacitive load listed.
adsp-21477 / adsp-21478 / adsp-21479 rev. c | page 59 of 76 | july 2013 figure 38. mlb timing (3-pin interface) table 53. mlb interface, 5-pin specifications parameter min typ max unit 5-pin characteristics t mlbclk mlb clock period 512 fs 256 fs 40 81 ns ns t mckl mlbclk low time 512 fs 256 fs 15 30 ns ns t mckh mlbclk high time 512 fs 256 fs 15 30 ns ns t mckr mlbclk rise time (v il to v ih )6ns t mckf mlbclk fall time (v ih to v il )6ns t mpwv 1 mlbclk pulse width variation 2 ns p-p t dsmcf 2 dat/sig input setup time 3 ns t dhmcf dat/sig input hold time 5 ns t mcdrv ds/do output data delay from mlbclk rising edge 8 ns t mcrdl 3 do/so low from mlbclk high 512 fs 256 fs 10 20 ns ns c mlb ds/do pin load 40 pf 1 pulse width variation is measured at 1.25 v by triggering on one edge of mlbclk and measuring the spread on the other edge, mea sured in ns peak -to-peak (p-p). 2 gate delays due to oring logic on the pins must be accounted for. 3 when a node is not driving valid data onto the bus, the mlbso and mlbdo output lines shall remain low. if the output lines can float at anytime, incl uding while in reset, external pull-down resistors are required to keep the outputs fr om corrupting the medialb signal lines when not being driven. t mckh mlbsig/ mlbdat (rx, input) t mckl t mckr mlbsig/ mlbdat (tx, output) t mcfdz t dsmcf mlbclk t mlbclk valid t dhmcf t mckf t mcdrv valid t mdzh
rev. c | page 60 of 76 | july 2013 adsp-21477 / adsp-21478 / adsp-21479 figure 39. mlb timing (5-pin interface) figure 40. mlb 3-pin and 5-pin ml bclk pulse width variation timing t mckh mlbsig/ mlbdat (rx, input) t mckl t mckr mlbso/ mlbdo (tx, output) t mcrdl t dsmcf mlbclk t mlbclk valid valid t dhmcf t mckf t mcdrv t mpwv t mpwv mlbclk
adsp-21477 / adsp-21478 / adsp-21479 rev. c | page 61 of 76 | july 2013 shift register table 54. shift register parameter min max unit timing requirements t ssdi sr_sdi setup before sr_sclk rising edge 7 ns t hsdi sr_sdi hold after sr_sclk rising edge 2 ns t ssdidai 1 dai_p08C01 (sr_sdi) setup before dai_p08C01 (sr_sclk) rising edge 7 ns t hsdidai 1 dai_p08C01 (sr_sdi) hold after dai_p08C01 (sr_sclk) rising edge 2 ns t ssck2lck 2 sr_sclk to sr_lat setup 2 ns t ssck2lckdai 1, 2 dai_p08C01 (sr_sclk) to dai_p08C01 (sr_lat) setup 2 ns t clrrem2sck removal time sr_clr to sr_sclk 3 t pclk C 5 ns t clrrem2lck removal time sr_clr to sr_lat 2 t pclk C 5 ns t clrw sr_clr pulse width 4 t pclk C 5 ns t sckw sr_sclk clock pulse width 2 t pclk C 2 ns t lckw sr_lat clock pulse width 2 t pclk C 5 ns f max maximum clock frequency sr_sclk or sr_lat f pclk ? 4mhz switching characteristics ns t dsdo1 3 sr_sdo hold after sr_sclk rising edge 3 ns t dsdo2 3 sr_sdo max. delay after sr_sclk rising edge 13 ns t dsdodai1 1, 3 sr_sdo hold after dai_p08C01 (sr_sclk) rising edge 3 ns t dsdodai2 1, 3 sr_sdo max. delay after dai_p08C01 (sr_sclk) rising edge 13 ns t dsdosp1 3, 4 sr_sdo hold after dai_p20C01 (sr_sclk) rising edge C2 ns t dsdosp2 3, 4 sr_sdo max. delay after dai_p20C01 (sr_sclk) rising edge 5 ns t dsdopcg1 3, 5, 6 sr_sdo hold after dai_p20C01 (sr_sclk) rising edge C2 ns t dsdopcg2 3, 5, 6 sr_sdo max. delay after dai_p20C01 (sr_sclk) rising edge 5 ns t dsdoclr1 3 sr_clr to sr_sdo min. delay 4 ns t dsdoclr2 3 sr_clr to sr_sdo max. delay 13 ns t dldo1 3 sr_ldo hold after sr_lat rising edge 3 ns t dldo2 3 sr_ldo max. delay after sr_lat rising edge 13 ns t dldodai1 3 sr_ldo hold after dai_p08C01 (sr_lat) rising edge 3 ns t dldodai2 3 sr_ldo max. delay after dai_p08C01 (sr_lat) rising edge 13 ns t dldosp1 3, 4 sr_ldo hold after dai_p20C01 (sr_lat) rising edge C2 ns t dldosp2 3, 4 sr_ldo max. delay after dai_p20C01 (sr_lat) rising edge 5 ns t dldopcg1 3, 5, 6 sr_ldo hold after dai_p20C01 (sr_lat) rising edge C2 ns t dldopcg2 3, 5, 6 sr_ldo max. delay after dai_p20C01 (sr_lat) rising edge 5 ns t dldoclr1 3 sr_clr to sr_ldo min. delay 4 ns t dldoclr2 3 sr_clr to sr_ldo max. delay 14 ns 1 any of the dai_p08C01 pin s can be routed to the shift register clock, latch clock and serial data input via the sru. 2 both clocks can be connected to the same cl ock source. if both clocks are connected to same clock source, then data in the 18-s tage shift register is a lways one cycle ahead of latch register data. 3 for setup/hold timing requirements of off-chip shift register interfacing devices. 4 sportx serial clock out, frame sync out, and serial data outp uts are routed to shift register block internally and are also rou ted onto dai_p20C01. 5 pcg serial clock output is routed to sport and shift register bl ock internally and are also routed onto dai_p20C01. the sports generate sr_lat and sdi internally. 6 pcg serial clock and frame sync outputs ar e routed to sport and shift register block internally and are also routed onto dai_p2 0C01. the sports generate sdi internally.
rev. c | page 62 of 76 | july 2013 adsp-21477 / adsp-21478 / adsp-21479 figure 41. sr_sdi setup, hold figure 42. sr_ sdo delay figure 43. sr_ldo delay dai_p08 - 01 or sr_sclk t ssdi ,t ssdidai t hsdi ,t hsdidai dai_p08 - 01 or sr_sdi sr_sdo sr_sclk or dai_p08-01 or dai_p20-01(spx_clk_o) or dai_p20-01(pcg_clkx_o) t dsdo1 t dsdo2 sr_sdo the timing parameters shown for t dsdo1 and t dsdo2 are valid for t dsdodai1 , t dsdosp1 , t dsdopcg1 , t dsdodai2 , t dsdosp2, and t dsdopcg2 sr_lat or dai_p08 - 01 or dai_p20 - 01 (spx_fs_o) or dai_p20 - 01 (pcg_fsx_o) t dldo1 t dldo2 sr_ldo the timing parameters shown for t dldo1 and t dldo2 are also valid for t dldodai1 , t dldodai2 , t dldosp1 , t dldosp2 , t dldopcg1 , and t dldopcg2 .
adsp-21477 / adsp-21478 / adsp-21479 rev. c | page 63 of 76 | july 2013 figure 44. sr_sclk to sr_lat setup, cl ocks pulse width and maximum frequency figure 45. shift register reset timing sr_sclk or dai_p08 - 01 sr_sdi or dai_p08 - 01 sr_ldo sr_lat or dai_p08 - 01 t ssck2lckdai t ssck2lck sr_sdclk or dai_p08 - 01 sr_ldo sr_lat or dai_p08 - 01 t dsdoclr2 t dsdoclr1 t dldoclr2 t dldoclr1 t clrw t clrrem2sck t clrrem2lck sr_clr sr_sdo
rev. c | page 64 of 76 | july 2013 adsp-21477 / adsp-21478 / adsp-21479 universal asynchronous receiver-transmitter (uart) portsreceive and transmit timing for information on the uart po rt receive and transmit opera- tions, see the adsp-214xx sharc hard ware reference manual . 2-wire interface (twi)receive and transmit timing for information on the twi receive and transmit operations, see the adsp-214xx sharc hardwa re reference manual . jtag test access port and emulation table 55. jtag test access port and emulation 88-lead lfcsp package all other packages unit parameter min max min max timing requirements t tck tck period 20 20 ns t stap tdi, tms setup before tck high 5 5 ns t htap tdi, tms hold after tck high 6 6 ns t ssys 1 1 system inputs = data15C0, clk_cfg1C0, reset , boot_cfg1C0, dai_px, dpi_px, flag3C0, mlbclk, mlbdat, mlbsig, sr_sclk, sr_clr , sr_sdi, and sr_lat. system inputs setup before tck high 7 7 ns t hsys 1 system inputs hold after tck high 18 18 ns t trstw trst pulse width 4 t ck 4 t ck ns switching characteristics t dtdo tdo delay from tck low 11.5 10.5 ns t dsys 2 2 system outputs = dai_px, dpi_px, addr23C0, ami_rd , ami_wr , flag3C0, sdras , sdcas , sdwe , sdcke, sda10, sddqm, sdcl k, mlbdat, mlbsig, mlbdo, mlbso, sr_sdo, sr_ldo, and emu . system outputs delay after tck low t ck 2 + 7 t ck 2 + 7 ns figure 46. ieee 1149.1 jtag test access port tck tms tdi tdo system inputs system outputs t tck t stap t htap t dtdo t ssys t hsys t dsys
adsp-21477 / adsp-21478 / adsp-21479 rev. c | page 65 of 76 | july 2013 output drive currents table 56 shows the driver types and the pins associated with each driver. figure 47 shows typical i-v characteristics for each driver. the curves represent the current drive capability of the output drivers as a function of output voltage. test conditions the ac signal specifications (timing parameters) appear in table 21 on page 29 through table 55 on page 64 . these include output disable time, output enable time, and capacitive loading. the timing specifications for the sharc apply for the voltage reference levels in figure 48 . timing is measured on signals wh en they cross the 1.5 v level as described in figure 49 . all delays (in nanoseconds) are mea- sured between the point that the first signal reaches 1.5 v and the point that the second signal reaches 1.5 v. capacitive loading output delays and holds are based on standard capacitive loads: 30 pf on all pins (see figure 48 ). figure 52 shows graphically how output delays and holds vary with load capacitance. the graphs of figure 50 , figure 51 , and figure 52 may not be linear outside the ranges shown for typical output delay vs. load capacitance and typical output rise time (20% to 80%, v = min) vs. load capacitance. table 56. driver types driver type associated pins a flag[0C3], ami_addr[23C0], data[15C0], ami_rd , ami_wr , ami_ack, ms[1-0] , sdras , sdcas , sdwe , sddqm, sdcke, sda10, emu , tdo, resetout , dpi[1C14], dai[1C20], wdtrsto , mlbdat, mlbsig, mlbso, mlbdo, mlbclk, sr_clr, sr_lat, sr_ldo[17C0], sr_sclk, sr_sdi bsdclk, rtclkout figure 47. typical drive at junction temperature sweep (v ddext ) voltage (v) 0 3.5 0.5 1.0 1.5 2.0 2.5 3.0 0 100 200 source/sink (v ddext ) current (ma) 150 50 - 100 - 200 - 150 - 50 v oh 3.13 v, 125 c v ol 3.13 v, 125 c type a type a type b type b figure 48. equivalent device loading for ac measurements (includes all fixtures) figure 49. voltage reference levels for ac measurements figure 50. typical output rise/fall time (20 to 80, v dd_ext = max) t1 zo = 50 : (impedance) td = 4.04 1.18 ns 2pf tester pin electronics 50 : 0.5pf 70 : 400 : 45 : 4pf notes: the worst case transmission line delay is shown and can be used for the output timing analysis to reflect the transmission line effect and must be considered. the transmission line (td) is for load only and does not affect the data sheet timing specifications. analog devices recommends using the ibis model timing for a given system requirement. if necessary, a system may incorporate external drivers to compensate for any timing differences. v load dut output 50 : input or output 1.5v 1.5v load capacitance (pf) 6 0 0 7 4 2 1 3 rise and fall times (ns) 125 200 100 25 175 50 75 150 5 y = 0.0331x + 0.2662 y = 0.0184x + 0.3065 y = 0.0421x + 0.2418 y = 0.0206x + 0.2271 type a drive fall type a drive rise type b drive fall type b drive rise
rev. c | page 66 of 76 | july 2013 adsp-21477 / adsp-21478 / adsp-21479 thermal characteristics the processor is rated for performance over the temperature range specified in operating conditions on page 21 . table 58 airflow measurements comp ly with jedec standards jesd51-2 and jesd51-6 and the junction-to-board measure- ment complies with jesd51-8. te st board design complies with jedec standards jesd51-7 (pbga) . the junction-to-case mea- surement complies with mil- std-883. all measurements use a 2s2p jedec test board. to determine the junction temperature of the device while on the application pcb, use: where: t j = junction temperature (c) t case = case temperature (c) measur ed at the top center of the package ? jt = junction-to-top (of package) characterization parameter is the typical value from table 58 p d = power dissipation values of ja are provided for pack age comparison and pcb design considerations. ja can be used for a first order approxi- mation of t j by the equation: where: t a = ambient temperature c values of jc are provided for pack age comparison and pcb design considerations when an external heatsink is required. note that the thermal characteristics values provided in table 58 are modeled values. figure 51. typical output rise/fall time (20% to 80%, v dd_ext = min) figure 52. typical output delay or hold vs. load capacitance (at ambient temperature) load capacitance (pf) 6 0 0 10 4 2 rise and fall times (ns) 25 200 150 50 75 100 125 175 y = 0.0567x + 0.482 y = 0.0367x + 0.4502 y = 0.0314x + 0.5729 type a drive fall type a drive rise type b drive rise type b drive fall 8 12 14 y = 0.0748x + 0.4601 load capacitance (pf) 3 0 3.5 2 1 0.5 1.5 rise and fall delay (ns) 2.5 y = 0.015x + 1.4889 y = 0.0088x + 1.6008 y = 0.0199x + 1.1083 y = 0.0102x + 1.2726 0 25 200 150 50 75 100 125 175 type a drive fall type a drive rise type b drive rise type b drive fall 4 4.5 t j t case ? jt p d ? ?? + = table 57. thermal characteristics for 88-lead lfcsp_vq parameter condition typical unit ? ja airflow = 0 m/s 22.6 c/w ? jma airflow = 1 m/s 18.2 c/w ? jma airflow = 2 m/s 17.3 c/w ? jc 7.9 c/w ? jt airflow = 0 m/s 0.22 c/w ? jmt airflow = 1 m/s 0.36 c/w ? jmt airflow = 2 m/s 0.44 c/w table 58. thermal characteristics for 100-lead lqfp_ep parameter condition typical unit ja airflow = 0 m/s 18.1 c/w jma airflow = 1 m/s 15.5 c/w jma airflow = 2 m/s 14.6 c/w jc 2.4 c/w jt airflow = 0 m/s 0.22 c/w jmt airflow = 1 m/s 0.36 c/w jmt airflow = 2 m/s 0.50 c/w table 59. thermal characteristics for 196-ball csp_bga parameter condition typical unit ja airflow = 0 m/s 29.0 c/w jma airflow = 1 m/s 26.1 c/w jma airflow = 2 m/s 25.1 c/w jc 8.8 c/w jt airflow = 0 m/s 0.23 c/w jmt airflow = 1 m/s 0.42 c/w jmt airflow = 2 m/s 0.52 c/w t j t a ? ja p d ? ?? + =
adsp-21477 / adsp-21478 / adsp-21479 rev. c | page 67 of 76 | july 2013 thermal diode the processors incorporate ther mal diode/s to monitor the die temperature. the thermal diode is a grounded collector, pnp bipolar junction transistor (bjt). the thd_p pin is connected to the emitter, and the thd_m pin is connected to the base of the transistor. these pins can be used by an external tempera- ture sensor (such as adm1021a or lm86 or others) to read the die temperature of the chip. the technique used by the extern al temperature sensor is to measure the change in vbe when the thermal diode is operated at two different currents. this is shown in the following equation: where: n = multiplication factor clos e to 1, depending on process variations k = boltzmann constant t = temperature (c) q = charge of the electron n = ratio of the two currents the two currents are usually in the range of 10 a to 300 a for the common temperature se nsor chips available. table 60 contains the thermal diod e specifications using the transistor model. ? v be n kt q ------ in(n) ? ? = table 60. thermal diode para meterstransistor model 1 symbol parameter min typ max unit i fw 2 forward bias current 10 300 a i e emitter current 10 300 a n q 3, 4 transistor ideality 1.012 1.015 1.017 r t 3, 5 series resistance 0.12 0.2 0.28 1 analog devices does not reco mmend operation of the the rmal diode under reverse bias. 2 analog devices does not reco mmend operation of the the rmal diode under reverse bias. 3 specified by design characterization. 4 the ideality factor, nq, represents the deviation from ideal diode behavior as exem plified by the diode equation: i c = i s (e qvbe/nqkt C 1) where i s = saturation current, q = electronic charge, v be = voltage across the diode, k = boltzmann co nstant, and t = absolute temperature (kelvin). 5 the series resistance (r t ) can be used for more acc urate readings as needed.
rev. c | page 68 of 76 | july 2013 adsp-21477 / adsp-21478 / adsp-21479 88-lfcsp_vq lead assignment table 61 lists the 88-lead lfcsp_ vq package lead names. table 61. 88-lead lfcsp_vq lead assignments (numerical by lead number) lead name lead no. lead name lead no. lead name lead no. lead name lead no. clk_cfg1 1 v dd_ext 23 dai_p10 45 v dd_int 67 boot_cfg0 2 dpi_p08 24 v dd_int 46 flag0 68 v dd_ext 3 dpi_p07 25 v dd_ext 47 v dd_int 69 v dd_int 4 dpi_p09 26 dai_p20 48 flag1 70 boot_cfg1 5 dpi_p10 27 v dd_int 49 flag2 71 gnd 6 dpi_p11 28 dai_p08 50 flag3 72 clk_cfg0 7 dpi_p12 29 dai_p04 51 gnd 73 v dd_int 8 dpi_p13 30 dai_p14 52 gnd 74 clkin 9 dai_p03 31 dai_p18 53 v dd_ext 75 xtal 10 dpi_p14 32 dai_p17 54 gnd 76 v dd_ext 11 v dd_int 33 dai_p16 55 v dd_int 77 v dd_int 12 dai_p13 34 dai_p15 56 trst 78 v dd_int 13 dai_p07 35 dai_p12 57 emu 79 resetout /runrstin 14 dai_p19 36 dai_p11 58 tdo 80 v dd_int 15 dai_p01 37 v dd_int 59 v dd_ext 81 dpi_p01 16 dai_p02 38 gnd 60 v dd_int 82 dpi_p02 17 v dd_int 39 thd_m 61 tdi 83 dpi_p03 18 v dd_ext 40 thd_p 62 tck 84 v dd_int 19 v dd_int 41 v dd_thd 63 v dd_int 85 dpi_p05 20 dai_p06 42 v dd_int 64 reset 86 dpi_p04 21 dai_p05 43 v dd_int 65 tms 87 dpi_p06 22 dai_p09 44 v dd_int 66 v dd_int 88 gnd 89* * lead no. 89 is the gnd supply (see figure 53 and figure 54 ) for the processor; this pad must be robustly connected to gnd in order for the processor to function.
adsp-21477 / adsp-21478 / adsp-21479 rev. c | page 69 of 76 | july 2013 figure 53 shows the top view of the 88-lead lfcsp_vq pin configuration. figure 54 shows the bottom view. figure 53. 88-lead lfcsp_vq le ad configuration (top view) pin 1 pin 22 pin 66 pin 45 pin 88 pin 67 pin 2 3 pin 44 pin 1 indicator ad s p-2147x 88 -lead lfc s p_vq top view figure 54. 88-lead lfcsp_vq lead configuration (bottom view) pin 66 pin 45 pin 1 pin 22 pin 67 pin 88 pin 44 pin 2 3 pin 1 indicator gnd pad (pin 8 9) ad s p-2147x 88 -lead lfc s p_vq bottom view
rev. c | page 70 of 76 | july 2013 adsp-21477 / adsp-21478 / adsp-21479 100-lqfp_ep lead assignment table 62 lists the 100-lead lqfp_ep lead names. table 62. 100-lead lqfp_ep lead assign ments (numerical by lead number) lead name lead no. lead name lead no. lead name lead no. lead name lead no. v dd_int 1v dd_ext 26 dai_p10 51 v dd_int 76 clk_cfg1 2 dpi_p08 27 v dd_int 52 flag0 77 boot_cfg0 3 dpi_p07 28 v dd_ext 53 v dd_int 78 v dd_ext 4v dd_int 29 dai_p20 54 v dd_int 79 v dd_int 5 dpi_p09 30 v dd_int 55 flag1 80 boot_cfg1 6 dpi_p10 31 dai_p08 56 flag2 81 gnd 7 dpi_p11 32 dai_p04 57 flag3 82 nc 8 dpi_p12 33 dai_p14 58 mlbclk 83 nc 9 dpi_p13 34 dai_p18 59 mlbdat 84 clk_cfg0 10 dai_p03 35 dai_p17 60 mlbdo 85 v dd_int 11 dpi_p14 36 dai_p16 61 v dd_ext 86 clkin 12 v dd_int 37 dai_p15 62 mlbsig 87 xtal 13 v dd_int 38 dai_p12 63 v dd_int 88 v dd_ext 14 v dd_int 39 v dd_int 64 mlbso 89 v dd_int 15 dai_p13 40 dai_p11 65 trst 90 v dd_int 16 dai_p07 41 v dd_int 66 emu 91 resetout /runrstin 17 dai_p19 42 v dd_int 67 tdo 92 v dd_int 18 dai_p01 43 gnd 68 v dd_ext 93 dpi_p01 19 dai_p02 44 thd_m 69 v dd_int 94 dpi_p02 20 v dd_int 45 thd_p 70 tdi 95 dpi_p03 21 v dd_ext 46 v dd_thd 71 tck 96 v dd_int 22 v dd_int 47 v dd_int 72 v dd_int 97 dpi_p05 23 dai_p06 48 v dd_int 73 reset 98 dpi_p04 24 dai_p05 49 v dd_int 74 tms 99 dpi_p06 25 dai_p09 50 v dd_int 75 v dd_int 100 gnd 101* * lead no. 101 is the gnd supply (see figure 55 and figure 56 ) for the processor; this pad must be robustly connected to gnd. mlb pins (pins 83, 84, 85, 87, and 89) are available for automoti ve models only. for non-automotive models, these pins should b e connected to ground (gnd).
adsp-21477 / adsp-21478 / adsp-21479 rev. c | page 71 of 76 | july 2013 figure 55 shows the top view conf iguration of the 100-lead lqfp_ep package. figure 56 shows the bottom view configura- tion of the 100-lead lqfp_ep package. figure 55. 100-lead lqfp_ep lead configuration (top view) figure 56. 100-lead lqfp_ep lead configuration (bottom view) lead 1 lead 25 lead 75 lead 51 lead 100 lead 76 lead 26 lead 50 lead 1 indicator adsp-2147x 100-lead lqfp_ep top view lead 75 lead 51 lead 1 lead 25 lead 76 lead 100 lead 50 lead 26 lead 1 indicator gnd pad (lead 101) adsp-2147x 100-lead lqfp_ep bottom view
rev. c | page 72 of 76 | july 2013 adsp-21477 / adsp-21478 / adsp-21479 196-bga ball assignment table 63. 196-ball csp_bga ball assi gnment (numerical by ball no.) ball no. signal ball no. signal ball no. signal ball no. signal ball no. signal a1 gnd d1 addr6 g1 xtal k1 dpi_p02 n1 dpi_p14 a2 sdcke d2 addr4 g2 sda10 k2 dpi_p04 n2 sr_ldo1 a3 sddqm d3 addr1 g3 addr11 k3 dpi_p05 n3 sr_ldo4 a4 sdras d4 clk_cfg0 g4 gnd k4 dpi_p09 n4 sr_ldo8 a5 sdwe d5 v dd_ext g5 v dd_int k5 v dd_int n5 sr_ldo10 a6 data12 d6 v dd_ext g6 gnd k6 gnd n6 dai_p01 a7 data13 d7 v dd_ext g7 gnd k7 gnd n7 sr_ldo9 a8 data10 d8 v dd_ext g8 gnd k8 gnd n8 dai_p02 a9 data9 d9 v dd_ext g9 gnd k9 gnd n9 sr_ldo13 a10 data7 d10 v dd_ext g10 v dd_int k10 v dd_int n10 sr_sclk a11 data3 d11 v dd_ext g11 v dd_ext k11 gnd n11 dai_p09 a12 data1 d12 addr14 g12 addr21 k12 dai_p16 n12 sr_sdi a13 data2 d13 addr20 g13 addr19 k13 dai_p18 n13 sr_ldo17 a14 gnd d14 wdt_clko g14 rtxo k14 dai_p15 n14 dai_p14 b1 addr0 e1 addr8 h1 addr13 l1 dai_p03 p1 gnd b2 clk_cfg1 e2 addr7 h2 addr12 l2 dpi_p10 p2 sr_ldo3 b3 boot_cfg0 e3 addr5 h3 addr10 l3 dpi_p08 p3 sr_ldo2 b4 tms e4 v dd_ext h4 addr17 l4 dpi_p06 p4 sr_ldo6 b5 reset e5 v dd_int h5 v dd_int l5 v dd_int p5 wdtrsto b6 data14 e6 v dd_int h6 gnd l6 v dd_int p6 dai_p19 b7 data11 e7 v dd_int h7 gnd l7 v dd_int p7 dai_p13 b8 data4 e8 v dd_int h8 gnd l8 v dd_int p8 sr_ldo11 b9 data8 e9 v dd_int h9 gnd l9 v dd_int p9 sr_ldo15 b10 data6 e10 v dd_int h10 v dd_int l10 v dd_int p10 sr_clr b11 data5 e11 v dd_ext h11 v dd_ext l11 dai_p10 p11 sr_lat b12 trst e12 ami_rd h12 boot_cfg2 l12 dai_p20 p12 sr_ldo14 b13 flag1 e13 addr22 h13 addr23 l13 dai_p17 p13 sr_ldo12 b14 data0 e14 flag2 h14 rtxi l14 dai_p04 p14 gnd c1 addr2 f1 clkin j1 dpi_p01 m1 dpi_p13 c2 addr3 f2 addr9 j2 dpi_p03 m2 dpi_p12 c3 rtclkout f3 boot_cfg1 j3 addr18 m3 sr_ldo0 c4 ms0 f4 nc j4 resetout /runrstin m4 dpi_p07 c5 sdcas f5 nc j5 v dd_int m5 dpi_p11 c6 data15 f6 gnd j6 gnd m6 sr_ldo5 c7 tck f7 gnd j7 gnd m7 sr_ldo7 c8 tdi f8 gnd j8 gnd m8 dai_p07 c9 sdclk f9 gnd j9 gnd m9 sr_ldo16 c10 emu f10 v dd_int j10 v ss_rtc m10 sr_sdo c11 tdo f11 v dd_ext j11 v dd_rtc m11 dai_p06 c12 flag3 f12 addr15 j12 dai_p11 m12 dai_p05 c13 addr16 f13 flag0 j13 ami_ack m13 dai_p08 c14 wdt_clkin f14 ami_wr j14 ms1 m14 dai_p12
adsp-21477 / adsp-21478 / adsp-21479 rev. c | page 73 of 76 | july 2013 outline dimensions the processors are available in 88-lead lfcsp_vq, 100-lead lqfp_ep and 196-ball csp_bga rohs compliant packages. for package assignment by model, see ordering guide on page 76 . figure 57. 88-lead lead frame chip scale package [lfcsp_vq 1 ] (cp-88-5) dimensions shown in millimeters 1 for information relating to the exposed pad on the cp-88-5 package, see the table endnote on page 68 . * compliant to jedec standards mo-220-vrrd except for minimum thickness and lead count. 1 22 66 45 23 44 88 67 0.50 0.40 0.30 0.30 0.23 0.18 10.50 ref 0.60 max 0.60 max 6.70 ref sq 0.50 bsc 0.138~0.194 ref 12 max seating plane top view exposed pad bottom view 0.70 0.65 0.60 0.045 0.025 0.005 pin 1 indicator 12.10 12.00 sq 11.90 11.85 11.75 sq 11.65 pin 1 indicator * 0.90 0.85 0.75 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. coplanarity 0.08
rev. c | page 74 of 76 | july 2013 adsp-21477 / adsp-21478 / adsp-21479 figure 58. 100-lead low pr ofile quad flat package, exposed pad [lqfp_ep 1 ] (sw-100-2) dimensions shown in millimeters 1 for information relating to the exposed pad on the sw-100-2 package, see the table endnote on page 70 . figure 59. 196-ball chip scale package, ball grid array [csp_bga] (bc-196-8) dimensions sho wn in millimeters compliant to jedec standards ms-026-bed-hd top view (pins down) bottom view (pins up) exposed pad 1 1 25 25 26 26 50 50 76 76 100 100 75 75 51 51 0.27 0.22 0.17 0.50 bsc lead pitch pin 1 16.20 16.00 sq 15.80 14.20 14.00 sq 13.80 6.00 bsc sq 12.00 ref for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.15 0.05 0.08 coplanarity 7 0 0.20 0.09 view a rotated 90 ccw 1.45 1.40 1.35 view a 1.60 max seating plane 0.75 0.60 0.45 1.00 ref compliant to jedec standards mo-275-ggab-1. 0.80 bsc 0.80 ref 0.70 ref 0.36 ref a b c d e f g 9 10 8 11 12 13 14 7 5 642 31 bottom view 10.40 bsc sq h j k l m n p detail a top view detail a coplanarity 0.12 0.50 0.45 0.40 ball diameter seating plane 12.10 12.00 sq 11.90 a1 ball corner a1 ball corner 0.35 nom 0.30 min 1.50 1.41 1.32 1.13 1.06 0.99
adsp-21477 / adsp-21478 / adsp-21479 rev. c | page 75 of 76 | july 2013 surface-mount design for industry-standard design recommendations, refer to ipc-7351, generic requirements for surface-mount design and land pattern standard. automotive products the adsp-21477, adsp-21478, an d adsp-21479 are available with controlled manufacturing to support the quality and reli- ability requirements of automotive applications. note that these automotive models may have specifications that differ from the commercial models, and designer s should review the product specifications section of this data sheet carefully. only the automotive grade products shown in table 64 are available for use in automotive applications. contact your local adi account representative for sp ecific product ordering infor- mation and to obtain the specific automotive reliability reports for these models. table 64. automotive product models model 1 temperature range 2 on-chip sram processor instruction rate (max) package description package option notes ad21477wycpz1axx C40c to +105c 2m bits 200 mhz 88-lead lfcsp_vq cp-88-5 ad21477wyswz1axx C40c to +105c 2m bits 200 mhz 100-lead lqfp_ep sw-100-2 ad21478wybcz2axx C40c to +105c 3m bits 200 mhz 88-lead lfcsp_vq cp-88-5 ad21478wycpz1axx C40c to +105c 3m bits 200 mhz 88-lead lfcsp_vq cp-88-5 ad21478wyswz2axx C40c to +105c 3m bits 266 mhz 100-lead lqfp_ep sw-100-2 ad21478wyswz2bxx C40c to +105c 3m bits 266 mhz 100-lead lqfp_ep sw-100-2 3, 4 ad21479wycpz1axx C40c to +105c 5m bits 200 mhz 88-lead lfcsp_vq cp-88-5 ad21479wycpz1bxx C40c to +105c 5m bits 200mhz 88-lead lfcsp_vq cp-88-5 3, 4 ad21479wyswz2axx C40c to +105c 5m bits 266 mhz 100-lead lqfp_ep sw-100-2 ad21479wyswz2bxx C40c to +105c 5m bits 266 mhz 100-lead lqfp_ep sw-100-2 3, 4 1 z = rohs compliant part. 2 referenced temperature is ambient temperature. the ambie nt temperature is not a sp ecification. please see operating conditions on page 21 for junction temperature (t j ) specification, which is the on ly temperature specification. 3 contains multichannel audio de coders from dolby and dts. 4 contains digital transmission co ntent protection (dtcp) from dtla. user must have current license from dtla to order this produ ct.
rev. c | page 76 of 76 | july 2013 adsp-21477 / adsp-21478 / adsp-21479 ? 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09017-0-7/13(c) ordering guide model 1 1 z =rohs compliant part. temperature range 2 2 referenced temperature is ambient temperature. the ambie nt temperature is not a sp ecification. please see operating conditions on page 21 for junction temperature (t j ) specification, which is the on ly temperature specification. on-chip sram processor instruction rate (max) package description package option adsp-21477kcpz-1a 0c to +70c 2m bits 200 mhz 88-lead lfcsp_vq cp-88-5 adsp-21477kswz-1a 0c to +70c 2m bits 200 mhz 100-lead lqfp_ep sw-100-2 adsp-21477bcpz-1a C40 ? c to +85 ? c 2m bits 200 mhz 88-lead lfcsp_vq cp-88-5 adsp-21478kcpz-1a 0c to +70c 3m bits 200 mhz 88-lead lfcsp_vq cp-88-5 adsp-21478bcpz-1a C40 ? c to +85 ? c 3m bits 200 mhz 88-lead lfcsp_vq cp-88-5 adsp-21478bbcz-2a C40c to +85c 3m bits 266 mhz 196-ball csp_bga bc-196-8 adsp-21478bswz-2a C40c to +85c 3m bits 266 mhz 100-lead lqfp_ep sw-100-2 adsp-21478kbcz-1a 0c to +70c 3m bits 200 mhz 196-ball csp_bga bc-196-8 adsp-21478kbcz-2a 0c to +70c 3m bits 266 mhz 196-ball csp_bga bc-196-8 adsp-21478kbcz-3a 0c to +70c 3m bits 300 mhz 196-ball csp_bga bc-196-8 ADSP-21478KSWZ-1A 0c to +70c 3m bits 200 mhz 100-lead lqfp_ep sw-100-2 adsp-21478kswz-2a 0c to +70c 3m bits 266 mhz 100-lead lqfp_ep sw-100-2 adsp-21479kcpz-1a 0c to +70c 5m bits 200 mhz 88-lead lfcsp_vq cp-88-5 adsp-21479bcpz-1a C40 ? c to +85 ? c 5m bits 200 mhz 88-lead lfcsp_vq cp-88-5 adsp-21479bbcz-2a C40c to +85c 5m bits 266 mhz 196-ball csp_bga bc-196-8 adsp-21479bswz-2a C40c to +85c 5m bits 266 mhz 100-lead lqfp_ep sw-100-2 adsp-21479kbcz-1a 0c to +70c 5m bits 200 mhz 196-ball csp_bga bc-196-8 adsp-21479kbcz-2a 0c to +70c 5m bits 266 mhz 196-ball csp_bga bc-196-8 adsp-21479kbcz-3a 0c to +70c 5m bits 300 mhz 196-ball csp_bga bc-196-8 adsp-21479kswz-1a 0c to +70c 5m bits 200 mhz 100-lead lqfp_ep sw-100-2 adsp-21479kswz-2a 0c to +70c 5m bits 266 mhz 100-lead lqfp_ep sw-100-2

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